A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining.
Jiun-In GuoChih-Da ChienChien-Chang LinPublished in: ISCAS (5) (2003)
Keyphrases
- low power
- variable length
- single chip
- power consumption
- low cost
- logic circuits
- discrete fourier transform
- fixed length
- gate array
- low power consumption
- high speed
- vlsi architecture
- ultra low power
- power dissipation
- fourier transform
- cmos technology
- frequency domain
- mixed signal
- radon transform
- bitstream
- parallel processing
- image processing
- machine learning
- real time