Shien-Chun Luo

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 3

Top Topics

Neighboring Pixels

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Shien-Chun Luo, Kuo-Chiang Chang, Po-Wei Chen, Zhao-Hong Chen
Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification. VLSI-DAT (2022)
Shien-Chun Luo
Customization of a Deep Learning Accelerator. VLSI-DAT (2019)
Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Jia-Hung Peng, Yuan-Hua Chu
MORAS: An energy-scalable system using adaptive voltage scaling. VLSI-DAT (2018)
Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu
A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2014)
Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. IEEE Trans. Circuits Syst. II Express Briefs (12) (2014)
Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou
An ultra-low-power adaptive-body-bias control for subthreshold circuits. VLSI-DAT (2014)
Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou
An ultra-low voltage hearing aid chip using variable-latency design technique. ISCAS (2014)
Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu
An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library. IEEE Trans. Circuits Syst. II Express Briefs (10) (2013)
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC (2013)
Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion. ISCAS (2012)
Shien-Chun Luo, Lih-Yih Chiou
A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing. IEEE Trans. Circuits Syst. II Express Briefs (6) (2010)
Lih-Yih Chiou, Shien-Chun Luo
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics. IEEE Trans. Very Large Scale Integr. Syst. 17 (11) (2009)
Lih-Yih Chiou, Shien-Chun Luo
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. ISCAS (2007)