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Chi-Ray Huang
ORCID
Publication Activity (10 Years)
Years Active: 2012-2021
Publications (10 Years): 4
Top Topics
Random Access Memory
Recognition Scheme
Low Voltage
Pulse Width
Top Venues
ISCAS
VLSI-DAT
IET Circuits Devices Syst.
IEEE Trans. Very Large Scale Integr. Syst.
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Publications
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Chi-Ray Huang
,
Lih-Yih Chiou
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM.
IEEE Trans. Very Large Scale Integr. Syst.
29 (8) (2021)
Lih-Yih Chiou
,
Chi-Ray Huang
,
Chang-Chieh Cheng
,
Jing-Yu Huang
,
Wei-Suo Ling
A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs.
VLSI-DAT
(2019)
Chi-Ray Huang
,
Lih-Yih Chiou
Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation.
IET Circuits Devices Syst.
12 (6) (2018)
Chi-Ray Huang
,
Kuan-Lin Wu
,
Chung-Han Wu
,
Lih-Yih Chiou
Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme.
ISCAS
(2018)
Lih-Yih Chiou
,
Chi-Ray Huang
,
Ming-Hung Wu
A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits.
ISCAS
(2014)
Shien-Chun Luo
,
Chi-Ray Huang
,
Lih-Yih Chiou
An ultra-low-power adaptive-body-bias control for subthreshold circuits.
VLSI-DAT
(2014)
Shien-Chun Luo
,
Chi-Ray Huang
,
Lih-Yih Chiou
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion.
ISCAS
(2012)