Chih-Wei Liu

Publication Activity (10 Years)

Years Active: 1999-2022
Publications (10 Years): 17

Top Topics

Fast Fourier Transform

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Faa-Jeng Lin, Chih-Wei Liu, Po-Lun Wang
Voltage Control of IPMSM Servo Drive in Constant Power Region With Intelligent Parameter Estimation. IEEE Access 10 (2022)
Ming-Chun Hsyu, Chih-Wei Liu, Chao-Hung Chen, Chao-Wei Chen, Wen-Chia Tsai
CSAnet: High Speed Channel Spatial Attention Network for Mobile ISP. CVPR Workshops (2021)
Chih-Wei Liu, Le-Ren Chang-Chien
Area Efficient High-Performance Digitally Controlled Power Management Unit. IEEE Trans. Ind. Electron. 68 (3) (2021)
Chun-Hsun Wu, Bu-Wei Chen, Wei-Hung Ko, Chih-Wei Liu, Le-Ren Chang-Chien
Phase sequence interchange scheme for suppressing transient cross regulation on the compensator controlled and non-compensator controlled single-inductor dual-output buck converter. IET Circuits Devices Syst. 15 (7) (2021)
Hong-Ke Lin, Pin-Han Lin, Chih-Wei Liu
Design of a High-Throughput and Area-Efficient Ultra-Long FFT Processor. VLSI-DAT (2020)
Chih-Wei Liu, Jia-Yu Wu, Kang-Chun Huang
A Low Latency NN-Based Cyclic Jacobi EVD Processor for DOA Estimation in Radar System. ISCAS (2020)
Chih-Wei Liu, Le-Ren Chang-Chien
Pipeline Signal Process Scheme for Saving Power Module Controllers in Power Management Unit. ISCAS (2020)
Chih-Wei Liu, Hung-Yu Chen, Le-Ren Chang-Chien
Auto-tuning charge balance control for improving transient response on buck converter. Int. J. Circuit Theory Appl. 48 (6) (2020)
Chih-Wei Liu, Chia-Kai Chan, Po-Hsiang Cheng, Hsin-Yuan Lin
FFT-Based Multirate Signal Processing for 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank. IEEE Trans. Circuits Syst. II Express Briefs (5) (2019)
Chia-Kai Chan, Hong-Ke Lin, Chih-Wei Liu
High-Throughput 64K-point FFT Processor for THz Imaging Radar System. VLSI-DAT (2019)
Ya-Chin Chung, Po-Hsiang Cheng, Chih-Wei Liu
Energy Efficient CNN Inference Accelerator Using Fast Fourier Transform. VLSI-DAT (2019)
Chih-Wei Liu, Shao-Kang Lo, Ai-Yun Hsieh, Yujong Hwang
Effects of banner Ad shape and the schema creating process on consumer internet browsing behavior. Comput. Hum. Behav. 86 (2018)
Chih-Wei Liu, Ai-Yun Hsieh, Shao-Kang Lo, Yujong Hwang
What consumers see when time is running out: Consumers' browsing behaviors on online shopping websites when under time pressure. Comput. Hum. Behav. 70 (2017)
Chi-Ming Lee, Yong-Jyun Huang, Chih-Wei Liu, Yarsun Hsu
DeAr: A framework for power-efficient and flexible embedded digital signal processor design. APCCAS (2016)
Chih-Wei Liu, Shih-Hao Ou, Kuo-Chiang Chang, Tsung-Ching Lin, Shin-Kai Chen
A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor. IEEE Trans. Computers 65 (4) (2016)
Huei-Shiuan Tang, Cheng-Yen Yang, Chih-Wei Liu, Chia-Cheng Chien
Binaural-cue-based noise reduction using multirate quasi-ANSI filter bank for hearing aids. APCCAS (2016)
Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou
A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems. IEEE ACM Trans. Audio Speech Lang. Process. 24 (8) (2016)
Shih-Hao Ou, Kuo-Chiang Chang, Chih-Wei Liu
An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids. Integr. 48 (2015)
Chia-Chen Hsu, Cheng-Yen Lin, Shin-Kai Chen, Chih-Wei Liu, Jenq Kuen Lee
Optimized memory access support for data layout conversion on heterogeneous multi-core systems. ESTIMedia (2014)
Chih-Wei Liu, Le-Ren Chang-Chien
Autonomous tuning method for realizing optimal adaptive voltage positioning scheme. ISCAS (2014)
Shin-Kai Chen, Cheng-Yu Hung, Ching-Chih Chen, Chih-Wei Liu
Parallelizing Complex Streaming Applications on Distributed Scratchpad Memory Multicore Architecture. Int. J. Parallel Program. 42 (6) (2014)
Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou
An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids. ICASSP (2014)
Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. IEEE Trans. Circuits Syst. II Express Briefs (12) (2014)
Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou
An ultra-low voltage hearing aid chip using variable-latency design technique. ISCAS (2014)
Kuo-Chiang Chang, Ching-Hao Lin, Chih-Wei Liu
Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. VLSI-DAT (2014)
Chih-Wei Liu, Kuo-Chiang Chang, Ming-Hsun Chuang, Ching-Hao Lin
10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Tsung-Ching Lin, Shin-Kai Chen, Chih-Wei Liu
A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applications. VLSI-DAT (2013)
Shin-Kai Chen, Chih-Wei Liu, Tsung-Yi Wu, An-Chi Tsai
Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM). IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2013)
Ju-Chi Tseng, Hsin-Cheng Tseng, Chih-Wei Liu, Chia Chun Shih, Kuo-Yu Tseng, Cheng-Yu Chou, Chia-Hsuan Yu, Fang-Sun Lu
A successful application of big data storage techniques implemented to criminal investigation for telecom. APNOMS (2013)
Cheng-Yen Yang, Wen-Sheng Chou, Kuo-Chiang Chang, Chih-Wei Liu, Tai-Shih Chi, Shyh-Jye Jou
Spatial-cue-based multi-band binaural noise reduction for hearing aids. SiPS (2013)
Shin-Kai Chen, Sheng-Yun Wu, Yu-Kai Yen, Chih-Wei Liu
Early Stage Codesign of Multi-PE SIMD Engine: A Case Study on Object Detection. ICPP Workshops (2012)
Ching-Hao Lin, Kuo-Chiang Chang, Ming-Hsun Chuang, Chih-Wei Liu
Design and implementation of 18-band Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aids. VLSI-DAT (2012)
Shih-Hao Ou, Che-Wei Yeh, Tay-Jyi Lin, Chih-Wei Liu
A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor. ISCAS (2012)
Ya-Ting Chang, Kuo-Chiang Chang, Yu-Ting Kuo, Chih-Wei Liu
Complexity-effective auditory compensation with a controllable filter for digital hearing aids. ASP-DAC (2012)
Cheng-Yu Chou, Chih-Wei Liu, Kuo-Yu Tseng, Chien-Wei Cheng, Fang-Sun Lu
Challenges of system virtualization. APNOMS (2012)
Kuo-Chiang Chang, Yu-Wen Chen, Yu-Ting Kuo, Chih-Wei Liu
A low power hearing aid computing platform using lightweight processing elements. ISCAS (2012)
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu
Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters. EURASIP J. Adv. Signal Process. 2011 (2011)
Meng-Ting Wang, Po-Chun Huang, Jenq Kuen Lee, Shang-Hong Lai, Jyh-Shing Roger Jang, Chun-Fa Chang, Chih-Wei Liu, Tei-Wei Kuo, Steve Liao
Support of Android lab modules for embedded system curriculum. WESE (2010)
Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, Chih-Wei Liu
Improving energy efficiency of functional units by exploiting their data-dependent latency. ISCAS (2010)
Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chih-Wei Liu
Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Kuo-Chiang Chang, Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu
Complexity-effective dynamic range compression for digital hearing aids. ISCAS (2010)
Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu
Collaborative voltage scaling with online STA and variable-latency datapath. ACM Great Lakes Symposium on VLSI (2010)
Shin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu
Parallel object detection on multicore platforms. SiPS (2009)
Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu
Ultra low-power ANSI S1.11 filter bank for digital hearing aids. ASP-DAC (2009)
Yu-Ting Kuo, Tay-Jyi Lin, Wei-Han Chang, Yueh-Tai Li, Chih-Wei Liu, Shuenn-Tsong Young
Complexity-effective auditory compensation for digital hearing aids. ISCAS (2008)
Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. J. Signal Process. Syst. 51 (3) (2008)
Shih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu
Multithreaded coprocessor interface for multi-core multimedia SoC. ASP-DAC (2008)
Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu
Improving datapathutilization of programmable DSP with composite functional units. ISCAS (2008)
Chih-Wei Liu, Chung-Chin Lu
A View of Gaussian Elimination Applied to Early-Stopped Berlekamp-Massey Algorithm. IEEE Trans. Commun. 55 (6) (2007)
Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu
Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. ISCAS (2007)
Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu
Self-Compensation Technique for Simplified Belief-Propagation Algorithm. IEEE Trans. Signal Process. 55 (6-2) (2007)
Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ISCAS (2007)
Chih-Wei Liu, Chung-Chin Lu
A View of Gaussian Elimination Applied to Early Stopped Berklekamp-Massey Algorithm. IEEE Trans. Commun. 55 (5) (2007)
Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. ASP-DAC (2007)
Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Wei-Han Chang, Chih-Wei Liu, Shuenn-Tsong Young
Design of ANSI S1.11 Filter Bank for Digital Hearing Aids. ICECS (2007)
Cheng-Fa Tsai, Chih-Wei Liu
KIDBSCAN: A New Efficient Data Clustering Algorithm. ICAISC (2006)
Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
A 52mW 1200MIPS compact DSP for multi-core media SoC. ASP-DAC (2006)
Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu
Carry Estimation for Two's Complement Fixed-Width Multipliers. SiPS (2006)
Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen
A Compact DSP Core with Static Floating-Point Arithmetic. J. VLSI Signal Process. 42 (2) (2006)
Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen
Programmable FIR filter with adder-based computing engine. ISCAS (2006)
Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen
Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) (2005)
Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen
Pipelining technique for energy-aware datapaths. ISCAS (2) (2005)
Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI (2005)
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
Architecture for area-efficient 2-D transform in H.264/AVC. ICME (2005)
Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
A compact DSP core with static floating-point unit & its microcode generation. ACM Great Lakes Symposium on VLSI (2004)
Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen
Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) (2004)
Yung-Chung Wang, Chih-Wei Liu, Chung-Chin Lu
Loss behavior in space priority queue with batch Markovian arrival process - discrete-time case. Perform. Evaluation 41 (4) (2000)
Chih-Wei Liu, Kuo-Tai Huang, Chung-Chin Lu
A Systolic Array Implementation of the Feng-Rao Algorithm. IEEE Trans. Computers 48 (7) (1999)