Chein-Wei Jen

Publication Activity (10 Years)

Years Active: 1986-2007
Publications (10 Years): 0

Publications

Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ISCAS (2007)
Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
A 52mW 1200MIPS compact DSP for multi-core media SoC. ASP-DAC (2006)
David Chih-Wei Chang, I-Tao Liao, Jenq Kuen Lee, Wen-Feng Chen, Shau-Yin Tseng, Chein-Wei Jen
PAC DSP Core and Application Processors. ICME (2006)
Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen
Programmable FIR filter with adder-based computing engine. ISCAS (2006)
Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen
A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding. IEEE Trans. Circuits Syst. Video Technol. 15 (2) (2005)
Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen
Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) (2005)
Kun-Bin Lee, Tzu-Chieh Lin, Chein-Wei Jen
An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC. IEEE Trans. Circuits Syst. Video Technol. 15 (5) (2005)
Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. IEEE Trans. Circuits Syst. Video Technol. 15 (3) (2005)
Hun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, Chein-Wei Jen
The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning. IEICE Trans. Electron. (5) (2005)
Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen
Pipelining technique for energy-aware datapaths. ISCAS (2) (2005)
Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI (2005)
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
Architecture for area-efficient 2-D transform in H.264/AVC. ICME (2005)
Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen
A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding. ISCAS (2) (2004)
Kun-Bin Lee, Hui-Cheng Hsu, Chein-Wei Jen
A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization. ISCAS (2) (2004)
Kun-Bin Lee, Hao-Yun Chin, Nelson Yen-Chung Chang, Hui-Cheng Hsu, Chein-Wei Jen
Optimal frame memory and data transfer scheme for MPEG-4 shape coding. IEEE Trans. Consumer Electron. 50 (1) (2004)
Kun-Bin Lee, Nelson Yen-Chung Chang, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen
A bandwidth and memory efficient MPEG-4 shape encoder. ASP-DAC (2004)
Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
A compact DSP core with static floating-point unit & its microcode generation. ACM Great Lakes Symposium on VLSI (2004)
Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen
Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) (2004)
Nelson Yen-Chung Chang, Kun-Bin Lee, Chein-Wei Jen
Trace-path analysis and performance estimation for multimedia application in embedded system. ISCAS (2) (2004)
Kun-Bin Lee, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen
QME: an efficient subsampling-based block matching algorithm for motion estimation. ISCAS (2) (2004)
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen
An Efficient VLIW DSP Architecture for Baseband Processing. ICCD (2003)
Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen
A memory efficient realization of cyclic convolution and its application to discrete cosine transform. ISCAS (4) (2003)
Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
Coefficient optimization for area-effective multiplier-less FIR filters. ICME (2003)
Wen-Chang Yeh, Chein-Wei Jen
Generalized Earliest-First Fast Addition Algorithm. IEEE Trans. Computers 52 (10) (2003)
Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
Area-effective FIR filter design for multiplier-less implementation. ISCAS (5) (2003)
Tay-Jyi Lin, Chin-Chi Chang, Tsung-Hsun Yang, Yu-Ming Chang, Chien-Hung Lin, Chen-Chia Lee, Hung-Yueh Lin, Chein-Wei Jen
Performance evaluation of ring-structure register file in multimedia applications. ICME (2003)
Yuan-Chung Lee, Chein-Wei Jen
Edge-preserving texture filtering for real-time rendering. Vis. Comput. 19 (1) (2003)
Wen-Chang Yeh, Chein-Wei Jen
High-speed and low-power split-radix FFT. IEEE Trans. Signal Process. 51 (3) (2003)
Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen
A new group distributed arithmetic design for the one dimensional discrete Fourier transform. ISCAS (1) (2002)
Yun-Tai Hsiao, Hung-Der Lin, Kun-Bin Lee, Chein-Wei Jen
High-speed memory-saving architecture for the embedded block coding in JPEG2000. ISCAS (5) (2002)
Tay-Jyi Lin, Chein-Wei Jen
CASCADE - configurable and scalable DSP environment. ISCAS (4) (2002)
Jen-Chieh Tuan, Tian-Sheuan Chang, Chein-Wei Jen
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture. IEEE Trans. Circuits Syst. Video Technol. 12 (1) (2002)
Bor-Sung Liang, Yuan-Chung Lee, Wen-Chang Yeh, Chein-Wei Jen
Index rendering: hardware-efficient architecture for 3-D graphics in multimedia system. IEEE Trans. Multim. 4 (3) (2002)
Tay-Jyi Lin, Chein-Wei Jen
An efficient 2-D DWT architecture via resource cycling. ISCAS (4) (2001)
Yuan-Chung Lee, Chein-Wei Jen
Improved quadratic normal vector interpolation for realistic shading. Vis. Comput. 17 (6) (2001)
Yuan-Chung Lee, Chein-Wei Jen
Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing. ISCAS (2) (2001)
Ilion Yi-Liang Hsiao, Ding-Hao Wang, Chein-Wei Jen
Power modeling and low-power design of content addressable memories. ISCAS (4) (2001)
Yuan-Chung Lee, Chein-Wei Jen
On-Line Polygon Refining Using a Low Computation Subdivision Algorithm. GMP (2000)
Wen-Chang Yeh, Chein-Wei Jen
High-Speed Booth Encoded Parallel Multiplier Design. IEEE Trans. Computers 49 (7) (2000)
Bor-Sung Liang, Wen-Chang Yeh, Yuan-Chung Lee, Chein-Wei Jen
Deferred lighting: a computation-efficient approach for real-time 3-D graphics. ISCAS (2000)
Tian-Sheuan Chang, Chin-Sheng Kung, Chein-Wei Jen
A simple processor core design for DCT/IDCT. IEEE Trans. Circuits Syst. Video Technol. 10 (3) (2000)
Ilion Yi-Liang Hsiao, Chein-Wei Jen
A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers. ISCAS (2000)
Wen-Chang Yeh, Chein-Wei Jen
A high performance carry-save to signed-digit recoder for fused addition-multiplication. ICASSP (2000)
Ching-Long Su, Chein-Wei Jen
Motion estimation using on-line arithmetic. ISCAS (2000)
Bor-Sung Liang, Chein-Wei Jen
Computation-effective 3-D graphics rendering architecture for embedded multimedia system. IEEE Trans. Consumer Electron. 46 (3) (2000)
Kun-Bin Lee, Chia-Hsing Lin, Chein-Wei Jen
Bus buffer modeling and optimization in video processing IP. ICECS (1999)
Jen-Chien Tuan, Chein-Wei Jen
An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement. Great Lakes Symposium on VLSI (1998)
Tian-Sheuan Chang, Chein-Wei Jen
Low power FIR filter realization with differential coefficients and input. ICASSP (1998)
Chih-Chin Chen, Chein-Wei Jen
A programmable concurrent video signal processor. ICIP (2) (1996)
Jinn-Wang Yeh, Wen-Jiunn Cheng, Chein-Wei Jen
VASS - A VLSI array system synthesizer. J. VLSI Signal Process. 12 (2) (1996)
Shifan Chang, Juin-Haur Hwang, Chein-Wei Jen
Scalable array architecture design for full search block matching. IEEE Trans. Circuits Syst. Video Technol. 5 (4) (1995)
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. ISCAS (1994)
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
A novel VLSI array design for the discrete Hartley transform using cyclic convolution. ICASSP (2) (1994)
Shifan Chang, Chein-Wei Jen, Charng Long Lee
A motion detection scheme for motion adaptive pro-scan conversion. Signal Process. Image Commun. 6 (4) (1994)
Jiann-Jenn Wang, Chein-Wei Jen
A High Throughput Systolic Design for QR Algorithm. ISCAS (1993)
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. ISCAS (1993)
Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen
A Multi-phase Shared Bus Structure for the Fast Fourier Transform. ISCAS (1993)
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
A New Array Architecture for Prime-Length Discrete Cosine Transform. IEEE Trans. Signal Process. 41 (1) (1993)
Chamg Long Lee, Chein-Wei Jen
Binary partition algorithms and VLSI architectures for median and rank order filtering. IEEE Trans. Signal Process. 41 (9) (1993)
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
A memory-based approach to design and implement systolic arrays for DFT and DCT. ICASSP (1992)
Chien-Piao Lan, Shih-Chieh Wen, Chein-Wei Jen
Efficient synthesis and high-speed implementation of look-ahead recursive filters. ICASSP (1992)
Chein-Wei Jen, Chi-Min Liu
Design of Two-Level Pipelined Systolic Array and its Application to Image. J. Circuits Syst. Comput. 2 (3) (1992)
Chein-Wei Jen, Ding-Ming Kwai
Data Flow Representation of Iterative Algorithms for Systolic Arrays. IEEE Trans. Computers 41 (3) (1992)
Chi-Min Liu, Chein-Wei Jen
A parallel adaptive algorithm for moving target detection and its VLSI array realization. IEEE Trans. Signal Process. 40 (11) (1992)
Tung-Hao Huang, Chi-Min Liu, Chein-Wei Jen
A high-level synthesizer for VLSI array architectures dedicated to digital signal processing. ICASSP (1991)
Chi-Min Liu, Chein-Wei Jen
Recursive algorithms for AR spectral estimation and their array realizations. ASAP (1990)
Chi-Min Liu, Bor-Shyong Yang, Chein-Wei Jen
Parallel adaptive algorithm for moving target indicator and its VLSI array realization. ICASSP (1990)
Chein-Wei Jen, Chi-Min Liu
Two-level pipeline design for image resampling. ICASSP (1989)
Chein-Wei Jen, Ding-Ming Kwai
Multi-dimensional parallel computing structures for regular iterative algorithms. Integr. 8 (3) (1989)
Sun-Yuan Kung, Chih-Wei Jim Chang, Chein-Wei Jen
Real-Time Configuration for Fault-Tolerant VLSI Array Processors. RTSS (1986)