A unified processor architecture for RISC & VLIW DSP.
Tay-Jyi LinChie-Min ChaoChia-Hsien LiuPi-Chen HsiaoShin-Kai ChenLi-Chun LinChih-Wei LiuChein-Wei JenPublished in: ACM Great Lakes Symposium on VLSI (2005)
Keyphrases
- instruction set
- level parallelism
- application specific
- systolic array
- floating point
- computer architecture
- computation intensive
- high speed
- signal processing
- parallel architecture
- hardware architecture
- memory subsystem
- embedded systems
- memory management
- texas instruments
- industry standard
- digital signal processing
- software architecture
- memory hierarchy
- memory access
- digital signal
- management system
- parallel algorithm
- instruction set architecture