Hierarchical instruction encoding for VLIW digital signal processors.
Chia-Hsien LiuTay-Jyi LinChie-Min ChaoPi-Chen HsiaoLi-Chun LinShin-Kai ChenChao-Wei HuangChih-Wei LiuChein-Wei JenPublished in: ISCAS (4) (2005)
Keyphrases
- digital signal processors
- level parallelism
- multimedia
- real time
- instructional design
- coarse to fine
- statistically significant
- fractal image compression
- field programmable gate array
- computer assisted instruction
- parallel processing
- graph cuts
- signal processing
- feature extraction
- image processing
- information systems
- machine learning