Login / Signup
Hierarchical instruction encoding for VLIW digital signal processors.
Chia-Hsien Liu
Tay-Jyi Lin
Chie-Min Chao
Pi-Chen Hsiao
Li-Chun Lin
Shin-Kai Chen
Chao-Wei Huang
Chih-Wei Liu
Chein-Wei Jen
Published in:
ISCAS (4) (2005)
Keyphrases
</>
digital signal processors
level parallelism
multimedia
real time
instructional design
coarse to fine
statistically significant
fractal image compression
field programmable gate array
computer assisted instruction
parallel processing
graph cuts
signal processing
feature extraction
image processing
information systems
machine learning