C. Bernard Shung

Publication Activity (10 Years)

Years Active: 1990-2008
Publications (10 Years): 0

Publications

Jeffrey M. Gilbert, Chinh H. Doan, Sohrab Emami, C. Bernard Shung
A 4-Gbps Uncompressed Wireless HD A/V Transceiver Chipset. IEEE Micro 28 (2) (2008)
Kuen-Rong Lo, Chung-Ju Chang, C. Bernard Shung
A neural fuzzy resource manager for hierarchical cellular systems supporting multimedia services. IEEE Trans. Veh. Technol. 52 (5) (2003)
Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. IEEE J. Solid State Circuits 36 (2) (2001)
Wei-Chang Tsai, C. Bernard Shung, Sheng-Jyh Wang
Two systolic architectures for modular multiplication. IEEE Trans. Very Large Scale Integr. Syst. 8 (1) (2000)
Kuen-Rong Lo, Chung-Ju Chang, Cooper Chang, C. Bernard Shung
A QoS-guaranteed fuzzy channel allocation controller for hierarchical cellular systems. IEEE Trans. Veh. Technol. 49 (5) (2000)
Hsie-Chia Chang, C. Bernard Shung
New serial architecture for the Berlekamp-Massey algorithm. IEEE Trans. Commun. 47 (4) (1999)
Hsie-Chia Chang, C. Bernard Shung
A (208, 192;8) Reed-Solomon decoder for DVD application. ICC (1998)
Kuen-Rong Lo, Chung-Ju Chang, Cooper Chang, C. Bernard Shung
A combined channel assignment mechanism for hierarchical cellular systems. Comput. Commun. 21 (13) (1998)
Yu-Sheng Lin, C. Bernard Shung
Quasi-pushout cell discarding. IEEE Commun. Lett. 1 (5) (1997)
Shu-Jen Fang, Yu-Sheng Lin, Shan-Chieh Yang, C. Bernard Shung
Reactive Bandwidth Arbitration for Priority and Multicasting Control in ATM Switching. ICC (3) (1997)
Wei-Chang Tsai, C. Bernard Shung
Event-Driven Power Estimation of CMOS Circuits. J. Circuits Syst. Comput. 7 (5) (1997)
Yu-Sheng Lin, C. Bernard Shung
Queue Management for Shared Buffer and Shared Multi-Buffer ATM Switches. INFOCOM (1996)
Yeong-Fong Lin, C. Bernard Shung
Fault-Tolerant Architectures for Shared Buffer Memory Switch. ISCAS (1994)
C. Bernard Shung, Horng-Dar Lin, Robert Cypher, Paul H. Siegel, Hemant K. Thapar
Area-efficient architectures for the Viterbi algorithm II. Applications. IEEE Trans. Commun. 41 (5) (1993)
Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen
A Multi-phase Shared Bus Structure for the Fast Fourier Transform. ISCAS (1993)
C. Bernard Shung, Horng-Dar Lin, Robert Cypher, Paul H. Siegel, Hemant K. Thapar
Area-efficient architectures for the Viterbi algorithm. I. Theory. IEEE Trans. Commun. 41 (4) (1993)
Robert Cypher, C. Bernard Shung
Generalized trace-back techniques for survivor memory management in the Viterbi algorithm. J. VLSI Signal Process. 5 (1) (1993)
Deborah C. Wang, C. Bernard Shung
Crossing distribution. EURO-DAC (1992)
Horng-Dar Lin, C. Bernard Shung
General in-place scheduling for the Viterbi algorithm. ICASSP (1991)
C. Bernard Shung, Rajeev Jain, Ken Rimey, Edward Wang, Mani B. Srivastava, Brian C. Richards, Erik Lettang, Syed Khalid Azim, Lars E. Thon, Paul N. Hilfinger, Jan M. Rabaey, Robert W. Brodersen
An integrated CAD system for algorithm-specific IC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (4) (1991)
Paul H. Siegel, C. Bernard Shung, Thomas D. Howell, Hemant K. Thapar
Exact bounds for Viterbi detector path metric differences. ICASSP (1991)
C. Bernard Shung, Paul H. Siegel, Hemant K. Thapar, Razmik Karabed
Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels. ICCD (1990)