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An ultra-low voltage hearing aid chip using variable-latency design technique.
Kuo-Chiang Chang
Shien-Chun Luo
Ching-Ji Huang
Chih-Wei Liu
Yuan-Hua Chu
Shyh-Jye Jou
Published in:
ISCAS (2014)
Keyphrases
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low voltage
high speed
cmos technology
design considerations
power consumption
power dissipation
chip design
case study
digital images
response time
machine vision
circuit design
power management