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Variation-aware and adaptive-latency accesses for reliable low voltage caches.

Po-Hao WangWei-Chung ChengYung-Hui YuTang-Chieh KaoChi-Lun TsaiPei-Yao ChangTay-Jyi LinJinn-Shyan WangTien-Fu Chen
Published in: VLSI-SoC (2013)
Keyphrases
  • low voltage
  • access latency
  • prefetching
  • design considerations
  • access patterns
  • computer vision
  • memory access
  • power line
  • image processing
  • response time