Jean-Loup Baer

Publication Activity (10 Years)

Years Active: 1968-2003
Publications (10 Years): 0

Joseph Fourier University, Grenoble, France (PHD)

Education History

Joseph Fourier University, Grenoble, France

PHD

Publications

Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal Sidhwaney
Memory Hierarchy Design for a Multiprocessor Look-up Engine. IEEE PACT (2003)
Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero
Cost-Effective Compiler Directed Memory Prefetching and Bypassing. IEEE PACT (2002)
Wayne A. Wong, Jean-Loup Baer
Modified LRU Policies for Improving Second-Level Cache Behavior. HPCA (2000)
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad
Characterizing processor architectures for programmable network interfaces. ICS (2000)
Peter van Vleet, Eric J. Anderson, Lindsay Brown, Jean-Loup Baer, Anna R. Karlin
Pursuing the Performance Potential of Dynamic Cache Line Sizes. ICCD (1999)
Patrick Crowley, Jean-Loup Baer
On the Use of Trace Sampling for Architectural Studies of Desktop Applications. SIGMETRICS (1999)
Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Thomas E. Anderson, Brian N. Bershad
Execution Characteristics of Desktop Applications on Windows NT. ISCA (1998)
Xiaohan Qin, Jean-Loup Baer
Optimizing Software Cache-coherent Cluster Architectures. SC (1998)
Jean-Loup Baer, Wen-Hann Wang
Retrospective: On the Inclusion Properties for Multi-Level Cache Hierarchies. 25 Years ISCA: Retrospectives and Reprints (1998)
Jean-Loup Baer, Wen-Hann Wang
On the Inclusion Properties for Multi-Level Cache Hierarchies. 25 Years ISCA: Retrospectives and Reprints (1998)
Xiaohan Qin, Jean-Loup Baer
A Performance Evaluation of Cluster-Based Architectures. SIGMETRICS (1997)
Xiaohan Qin, Jean-Loup Baer
On the Use and Performance of Explicit Communication Primitives in Cache-Coherent Multiprocessor Systems. HPCA (1997)
Theodore H. Romer, Dennis Lee, Geoffrey M. Voelker, Alec Wolman, Wayne A. Wong, Jean-Loup Baer, Brian N. Bershad, Henry M. Levy
The Structure and Performance of Interpreters. ASPLOS (1996)
Tien-Fu Chen, Jean-Loup Baer
Effective Hardware Based Data Prefetching for High-Performance Processors. IEEE Trans. Computers 44 (5) (1995)
Craig Anderson, Jean-Loup Baer
Two Techniques for Improving Performance on Bus-Based Multiprocessors. HPCA (1995)
Xiaohan Qin, Jean-Loup Baer
A comparative study of conservative and optimistic trace-driven simulations. Annual Simulation Symposium (1995)
Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grunwald
Instruction Cache Fetch Policies for Speculative Execution. ISCA (1995)
Craig Anderson, Jean-Loup Baer
Two techniques for improving performance on bus-based multiprocessors. Future Gener. Comput. Syst. 11 (6) (1995)
Sang Lyul Min, Jae H. Nam, Myung Soon Park, Jean-Loup Baer
Cache-Based Data Distribution Constrained Scheduling. Int. J. High Speed Comput. 6 (1) (1994)
Tien-Fu Chen, Jean-Loup Baer
A Performance Study of Software and Hardware Data Prefetching Schemes. ISCA (1994)
Richard N. Zucker, Jean-Loup Baer
Software versus Hardware Coherence: Performance versus Cos. HICSS (1) (1994)
Xiaohan Qin, Jean-Loup Baer
A Parallel Trace-driven Simulator: Implementation and Performance. ICPP (2) (1994)
Jean-Loup Baer, Tien-Fu Chen
An Evaluation of Hardware and Software Data Prefetching. Applications in Parallel and Distributed Computing (1994)
Craig Anderson, Jean-Loup Baer
A Multi-Level Hierarchical Cache Coherence Protocol for Multiprocessors. IPPS (1993)
Jonathan Bertoni, Jean-Loup Baer, Wen-Hann Wang
Scaling shared-bus multiprocessors with multiple buses and shared caches: a performance study. Microprocess. Microsystems 16 (7) (1992)
Richard N. Zucker, Jean-Loup Baer
A Performance Study of Memory Consistency Models. ISCA (1992)
Sang Lyul Min, Jean-Loup Baer
Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps. IEEE Trans. Parallel Distributed Syst. 3 (1) (1992)
Tien-Fu Chen, Jean-Loup Baer
Reducing Memory Latency via Non-blocking and Prefetching Caches. ASPLOS (1992)
Jean-Loup Baer, Tien-Fu Chen
An effective on-chip preloading scheme to reduce data access penalty. SC (1991)
Wen-Hann Wang, Jean-Loup Baer
Efficient Trace-Driven Simulation Methods for Cache Performance Analysis. ACM Trans. Comput. Syst. 9 (3) (1991)
Jean-Loup Baer, Richard N. Zucker
On Synchronization Patterns in Parallel Programs. ICPP (2) (1991)
Sang Lyul Min, Jean-Loup Baer, Hyoung-Joo Kim
An efficient caching support for critical sections in large-scale shared-memory multiprocessors. ICS (1990)
Sang Lyul Min, Jean-Loup Baer
A Performance Comparison of Directory-based and Timestamp-based Cache Coherence Schemes. ICPP (1) (1990)
Wen-Hann Wang, Jean-Loup Baer
Efficient Trace-Driven Simulation Methods for Cache Performance Analysis. SIGMETRICS (1990)
Jean-Loup Baer, Yi-Bing Lin
Improving Quicksort Performance with a Codewort Data Structure. IEEE Trans. Software Eng. 15 (5) (1989)
Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan
Extending the Memory Hierarchy into Multiprocessor Interconnection Networks: A Performance Analysis. ICPP (1) (1989)
Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan
Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks. ISCA (1989)
Wen-Hann Wang, Jean-Loup Baer, Henry M. Levy
Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy. ISCA (1989)
Jean-Loup Baer, Wen-Hann Wang
Multilevel Cache Hierarchies: Organizations, Protocols, and Performance. J. Parallel Distributed Comput. 6 (3) (1989)
Sang Lyul Min, Jean-Loup Baer
A Timestamp-based Cache Coherence Scheme. ICPP (1) (1989)
Jean-Loup Baer, Meei-Chiueh Liem, Larry McMurchie, Rudolf Nottrott, Lawrence Snyder, Wayne Winder
A Notation for Describing Multiple Views of VLSI Circuits. DAC (1988)
Jean-Loup Baer, Wen-Hann Wang
On the Inclusion Properties for Multi-Level Cache Hierarchies. ISCA (1988)
Jean-Loup Baer, Wen-Hann Wang
Architectural Choices for Multi-level Cache Hierarchies. ICPP (1987)
Jean-Loup Baer
Modelling Architectural Features with Petri Nets. Advances in Petri Nets (1986)
James K. Archibald, Jean-Loup Baer
Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model. ACM Trans. Comput. Syst. 4 (4) (1986)
Sai Choi Kwan, Jean-Loup Baer, G. Zick, T. Snyder
Parallel Tag-Distribution Sort. ICPP (1985)
Sai Choi Kwan, Jean-Loup Baer
The I/O Performance of Multiway Mergesort and Tag Sort. IEEE Trans. Computers 34 (4) (1985)
James K. Archibald, Jean-Loup Baer
An Economical Solution to the Cache Coherence Problem. ISCA (1984)
Jean-Loup Baer
Computer Architecture. Computer 17 (10) (1984)
Hung-Chang Du, Jean-Loup Baer
On the Performance of Interleaved Memories with Non-Uniform Access Probabilities. ICPP (1983)
Jean-Loup Baer, Hung-Chang Du, Richard E. Ladner
Binary Search in a Multiprocessing Environment. IEEE Trans. Computers 32 (7) (1983)
Jean-Loup Baer, Georges Gardarin, Claude Girault, Gérard Roucairol
The Two-Step Commitment Protocol: Modeling, Specification and Proof Methodology. ICSE (1981)
Ahmed S. Zaki, Jean-Loup Baer
Query costs in HB(1) trees versus 2-3 trees. Int. J. Parallel Program. 10 (6) (1981)
Jean-Loup Baer, Barbara Koyama
On the Minimization of the Width of the Control Memory of Microprogammed Processors. IEEE Trans. Computers 28 (4) (1979)
Jean-Loup Baer
Software control and program design issues for alterable architectures. COMPSAC (1978)
Jean-Loup Baer, Carla Schlatter Ellis
Model, Design, and Evaluation of a Compiler for a Parallel Processing Environment. IEEE Trans. Software Eng. 3 (6) (1977)
Jean-Loup Baer, John E. Jensen
Simulation of Large Parallel Systems: Modelling of Tasks. Performance (1977)
Jean-Loup Baer, M. Fries
On the Efficiency of Some List Marketing Algorithms. IFIP Congress (1977)
Jean-Loup Baer, B. Schwab
A Comparison of Tree-Balancing Algorithms. Commun. ACM 20 (5) (1977)
Jean-Loup Baer, Gary R. Sager
Dynamic Improvement of Locality in Virtual Memory Systems. IEEE Trans. Software Eng. 2 (1) (1976)
Jean-Loup Baer, Gary R. Sager
Correction to "Dynamic Improvement of Locality in Virtual Memory Systems". IEEE Trans. Software Eng. 2 (2) (1976)
G. Kampen, Jean-Loup Baer
The Formal Definition of Semantics by String Automata. Comput. Lang. 1 (2) (1976)
John E. Jensen, Jean-Loup Baer
A Model of Interference in a Shared Resource Multiprocessor. ISCA (1976)
Jean-Loup Baer
Multiprocessing Systems. IEEE Trans. Computers 25 (12) (1976)
Jean-Loup Baer
Weight-balanced trees. AFIPS National Computer Conference (1975)
Jean-Loup Baer
On Program Placement in a Directly Executable Hierarchy of Memories. IEEE Trans. Computers 23 (8) (1974)
Jean-Loup Baer
Models for the design, simulation, and performance of distributed-function architecture. Computer 7 (3) (1974)
Jean-Loup Baer
A Survey of Some Theoretical Aspects of Multiprocessing. ACM Comput. Surv. 5 (1) (1973)
Jean-Loup Baer, Robert Caughey
Segmentation and optimization of programs from cyclic structure analysis. AFIPS Spring Joint Computing Conference (1972)
Jean-Loup Baer, Daniel P. Bovet, Gerald Estrin
Legality and Other Properties of Graph Models of Computations. J. ACM 17 (3) (1970)
Jean-Loup Baer, Gerald Estrin
Bounds for Maxium Parallelism in a Bilogic Graph Model of Computations. IEEE Trans. Computers 18 (11) (1969)
Jean-Loup Baer, Daniel P. Bovet
Compilation of arithmetic expressions for parallel computations. IFIP Congress (1) (1968)

Jean-Loup Baer.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Jean-Loup Baer