A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications.
Win-San KhwaMeng-Fan ChangJau-Yi WuMing-Hsiu LeeTzu-Hsiang SuKeng-Hao YangTien-Fu ChenTien-Yen WangHsiang-Pang LiMatthew J. BrightSkySangBum KimHsiang-Lam LungChung LamPublished in: IEEE J. Solid State Circuits (2017)