all-digital delay-locked loop in 65-nm CMOS.

Chun-Yuan Cheng Jinn-Shyan Wang Pei-Yuan Chou Shiou-Ching Chen Chi-Tien Sun Yuan-Hua Chu Tzu-Yi Yang

Published in: A-SSCC (2014)

Keyphrases

metal oxide semiconductor
circuit design
cmos technology
low cost
power dissipation
high speed
integrated circuit
cmos image sensor
mixed signal
silicon on insulator
nm technology
low power
analog vlsi
digital objects
vlsi circuits
infrared
analog to digital converter