A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture.
Jinn-Shyan WangChun-Yuan ChengPei-Yuan ChouTzu-Yi YangPublished in: IEEE J. Solid State Circuits (2015)
Keyphrases
- low power
- mixed signal
- wide range
- vlsi architecture
- power consumption
- low cost
- high speed
- vlsi circuits
- power dissipation
- cmos technology
- multi channel
- analog to digital converter
- single chip
- wireless transmission
- high power
- cmos image sensor
- digital signal processing
- logic circuits
- real time
- nm technology
- low power consumption
- power reduction
- image sensor
- low voltage
- digital circuits
- ultra low power