Chia-Lin Yang

ORCID

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 41

Top Venues

Publications

Mikail Yayla, Simon Thomann, Md Mazharul Islam, Ming-Liang Wei, Shu-Yin Ho, Ahmedullah Aziz, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch
Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories. VTS (2023)
Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES (2023)
Xuan-Jun Chen, Cynthia Kuan, Chia-Lin Yang
Unified Agile Accuracy Assessment in Computing-in-Memory Neural Accelerators by Layerwise Dynamical Isometry. DAC (2023)
Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang
Tensor Movement Orchestration in Multi-GPU Training Systems. HPCA (2023)
Chia-Lin Yang
Understanding Computer Architecture Sustainability. Computer 56 (9) (2023)
Mikail Yayla, Simon Thomann, Ming-Liang Wei, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch
HW/SW Codesign for Robust and Efficient Binarized SNNs by Capacitor Minimization. CoRR (2023)
Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Hussam Amrouch, Chia-Lin Yang
Impact of Non-Volatile Memory Cells on Spiking Neural Network Annealing Machine With In-Situ Synapse Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (11) (2023)
Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo
Efficient Bad Block Management with Cluster Similarity. HPCA (2022)
Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai
This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. ASP-DAC (2022)
Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. ASP-DAC (2022)
Chia-Lin Yang
A Forward Speculative Interference Attack. Computer 55 (6) (2022)
Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li
Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging. NVMSA (2022)
Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators. ACM Trans. Embed. Comput. Syst. 21 (3) (2022)
Xuan Sun, Hu Wan, Qiao Li, Chia-Lin Yang, Tei-Wei Kuo, Chun Jason Xue
RM-SSD: In-Storage Computing for Large-Scale Recommendation Inference. HPCA (2022)
Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Chia-Lin Yang, Hussam Amrouch
Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization. ICCAD (2021)
Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang
Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning. ISPASS (2021)
Hu Wan, Xuan Sun, Yufei Cui, Chia-Lin Yang, Tei-Wei Kuo, Chun Jason Xue
FlashEmbedding: storing embedding tables in SSD for large-scale recommender systems. APSys (2021)
Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo
Future Computing Platform Design: A Cross-Layer Design Approach. DATE (2021)
Yu-Sheng Lin, Wei-Chao Chen, Chia-Lin Yang, Shao-Yi Chien
A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads. ISCAS (2021)
Yu-Sheng Lin, Wei-Chao Chen, Chia-Lin Yang, Shao-Yi Chien
A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads. CoRR (2021)
Jun-Liang Lin, Tsung-Ting Hsieh, Yi-An Tung, Xuan-Jun Chen, Yu-Chun Hsiao, Chia-Lin Yang, Tyng-Luh Liu, Chien-Yu Chen
ezGeno: an automatic model selection package for genomic data analysis. Bioinform. 38 (1) (2021)
Ming-Liang Wei, Hussam Amrouch, Cheng-Lin Sung, Hang-Ting Lue, Chia-Lin Yang, Keh-Chung Wang, Chih-Yuan Lu
Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses. IRPS (2021)
Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. DAC (2020)
Chien-I Lee, Meng-Yao Lin, Chia-Lin Yang, Yen-Kuang Chen
Iotbench: A Benchmark Suite for Intelligent Internet of Things Edge Devices. ICIP (2019)
Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. ISCA (2019)
Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang
The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper. ICCAD (2019)
Cheng Ji, Lun Wang, Qiao Li, Congming Gao, Liang Shi, Chia-Lin Yang, Chun Jason Xue
Fair Down to the Device: A GC-Aware Fair Scheduler for SSD. NVMSA (2019)
Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. ICCAD (2018)
Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. DAC (2018)
Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang
LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling. CoRR (2018)
Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang
Enabling fast preemption via Dual-Kernel support on GPUs. ASP-DAC (2017)
Chun-Hao Lai, Jishen Zhao, Chia-Lin Yang
Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach. DAC (2017)
Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. IEEE Comput. Archit. Lett. 16 (2) (2017)
Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang
Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives. IEEE Trans. Computers 66 (8) (2017)
Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. ISPASS (2017)
David Garrett, Chia-Lin Yang
Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED). IEEE Des. Test 34 (6) (2017)
Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang
A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration. ACM Trans. Design Autom. Electr. Syst. 22 (2) (2017)
David Garrett, Chia-Lin Yang
Message from the general co-chairs. ISLPED (2017)
Renhai Chen, Zili Shao, Chia-Lin Yang, Tao Li
MCSSim: A memory channel storage simulator. ASP-DAC (2016)
Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality. IEEE Trans. Computers 65 (4) (2016)
Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture. DAC (2016)
Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li
Fine-grained write scheduling for PCM performance improvement under write power budget. ISLPED (2015)
Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang
Improving DRAM latency with dynamic asymmetric subarray. MICRO (2015)
Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. RACS (2015)
Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. NVMSA (2015)
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. ACM Trans. Archit. Code Optim. 12 (2) (2015)
Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-Wen Hsueh, Naehyuck Chang
System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach. ACM Trans. Embed. Comput. Syst. 14 (1) (2015)
Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. DAC (2014)
Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Shun-Chih Yu, Cheng-Yuan Michael Wang
NVM duet: unified working memory and persistent store architecture. ASPLOS (2014)
Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky
Full system simulation framework for integrated CPU/GPU architecture. VLSI-DAT (2014)
Martin Dimitrov, Yung-Hsiang Lu, Chia-Lin Yang
Guest Editors' Introduction: Cloud Computing for Embedded Systems. IEEE Des. Test 31 (3) (2014)
Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. ISLPED (2013)
Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang
Thermal coupling aware task migration using neighboring core search for many-core systems. VLSI-DAT (2013)
Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen
DuraCache: a durable SSD cache using MLC NAND flash. DAC (2013)
Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang
Memory access aware power gating for MPSoCs. ASP-DAC (2012)
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
SECRET: Selective error correction for refresh energy reduction in DRAMs. ICCD (2012)
Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng
A cycle-level SIMT-GPU simulation framework. ISPASS (2012)
Ren-Shuo Liu, Chia-Lin Yang, Wei Wu
Optimizing NAND flash-based SSDs via retention relaxation. FAST (2012)
Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. ICCAD (2012)
Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang
Age-based PCM wear leveling with nearly zero search cost. DAC (2012)
Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems. IEEE Trans. Computers 60 (6) (2011)
Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen, Yu-Jung Cheng
Power gating strategies on GPUs. ACM Trans. Archit. Code Optim. 8 (3) (2011)
James C. Chen, Kou-Huang Chen, Chien-Hsin Lin, Chia-Wen Chen, Chia-Lin Yang
A Study of a Heuristic Capacity Planning Algorithm for Weapon Production System. Int. J. Electron. Bus. Manag. 9 (1) (2011)
Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang
Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (9) (2011)
Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang
A SAT-based routing algorithm for cross-referencing biochips. SLIP (2011)
Sangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang
Dynamic thermal management for networked embedded systems under harsh ambient temperature variation. ISLPED (2010)
Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang
Hierarchical memory scheduling for multimedia MPSoCs. ICCAD (2010)
Ren-Shuo Liu, Yun-Cheng Tsai, Chia-Lin Yang
Parallelization and characterization of GARCH option pricing on GPUs. IISWC (2010)
Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang
Memory Latency Reduction via Thread Throttling. MICRO (2010)
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
PM-COSYN: PE and memory co-synthesis for MPSoCs. DATE (2010)
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
T-trees: A tree-based representation for temporal and three-dimensional floorplanning. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang, Yu-Jung Cheng
A Predictive Shutdown Technique for GPU Shader Processors. IEEE Comput. Archit. Lett. 8 (1) (2009)
Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. ISLPED (2009)
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (9) (2009)
Sung-Wen Wang, Shu-Sian Yang, Hong-Ming Chen, Chia-Lin Yang, Ja-Ling Wu
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters. J. Signal Process. Syst. 57 (2) (2009)
Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design. J. Syst. Archit. 55 (5-6) (2009)
Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu
Thermal modeling for 3D-ICs with integrated microchannel cooling. ICCAD (2009)
Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng
Energy-Aware Flash Memory Management in Virtual Memory System. IEEE Trans. Very Large Scale Integr. Syst. 16 (8) (2008)
Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (4) (2008)
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (11) (2008)
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
A progressive-ILP based routing algorithm for cross-referencing biochips. DAC (2008)
Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King
Energy-efficient real-time task scheduling with task rejection. DATE (2007)
Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su
An architectural co-synthesis algorithm for energy-aware network-on-chip design. SAC (2007)
Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED (2007)
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. 12 (4) (2007)
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen
Cache leakage control mechanism for hard real-time systems. CASES (2007)
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD (2007)
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. ACM J. Emerg. Technol. Comput. Syst. 3 (3) (2007)
Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang
Efficient obstacle-avoiding rectilinear steiner tree construction. ISPD (2007)
Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME (2007)
Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang
A Space-Efficient Caching Mechanism for Flash-Memory Address Translation. ISORC (2006)
Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King
Hierarchical value cache encoding for off-chip data bus. ISLPED (2006)
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
Placement of digital microfluidic biochips using the t-tree formulation. DAC (2006)
Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang
An energy-efficient virtual memory system with flash memory as the secondary storage. ISLPED (2006)
Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen
Branch Behavior Characterization for Multimedia Applications. Asia-Pacific Computer Systems Architecture Conference (2006)
Chia-Lin Yang, Hong-Wei Tseng, Chia-Chiang Ho, Ja-Ling Wu
Software-Controlled Cache Architecture for Energy Efficiency. IEEE Trans. Circuits Syst. Video Technol. 15 (5) (2005)
Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang
Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED (2005)
Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung
Cache Leakage Management for Multi-programming Workloads. Asia-Pacific Computer Systems Architecture Conference (2005)
Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen
Reconfigurable Platform for Content Science Research. RTCSA (2005)

Chia-Lin Yang.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Chia-Lin Yang