A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.
Ye-Jyun LinChia-Lin YangHsiang-Pang LiCheng-Yuan Michael WangPublished in: NVMSA (2015)
Keyphrases
- main memory
- memory access
- memory subsystem
- memory hierarchy
- virtual memory
- dynamic random access memory
- memory management
- database management systems
- instruction set
- external memory
- data access
- cache conscious
- data structure
- ibm zenterprise
- secondary storage
- embedded dram
- multithreading
- index structure
- operating system
- management system
- cache misses
- random access memory
- buffer pool
- input output
- mobile devices
- flash memory
- computing power
- garbage collection
- read write
- buffer management
- design considerations
- access patterns
- high density
- smart phones
- mobile applications