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Ye-Jyun Lin
Publication Activity (10 Years)
Years Active: 2010-2017
Publications (10 Years): 1
Top Topics
Multithreading
Embedded Dram
Buffer Pool
Memory Access
Top Venues
ACM Trans. Embed. Comput. Syst.
ASP-DAC
NVMSA
ACM Trans. Design Autom. Electr. Syst.
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Publications
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Ye-Jyun Lin
,
Chia-Lin Yang
,
Hsiang-Pang Li
,
Cheng-Yuan Michael Wang
A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration.
ACM Trans. Design Autom. Electr. Syst.
22 (2) (2017)
Ye-Jyun Lin
,
Chia-Lin Yang
,
Hsiang-Pang Li
,
Cheng-Yuan Michael Wang
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.
NVMSA
(2015)
Ye-Jyun Lin
,
Chia-Lin Yang
,
Jiao-Wei Huang
,
Tay-Jyi Lin
,
Chih-Wen Hsueh
,
Naehyuck Chang
System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach.
ACM Trans. Embed. Comput. Syst.
14 (1) (2015)
Ye-Jyun Lin
,
Chia-Lin Yang
,
Jiao-Wei Huang
,
Naehyuck Chang
Memory access aware power gating for MPSoCs.
ASP-DAC
(2012)
Ye-Jyun Lin
,
Chia-Lin Yang
,
Tay-Jyi Lin
,
Jiao-Wei Huang
,
Naehyuck Chang
Hierarchical memory scheduling for multimedia MPSoCs.
ICCAD
(2010)