Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture.

Po-Han Wang Cheng-Hsuan Li Chia-Lin Yang

Published in: DAC (2016)

Keyphrases

multi core architecture
prefetching
energy efficient
hit ratio
response time
digital signal processor
replacement policy
access patterns
single instruction multiple data
multi core processors
data access
memory bandwidth
web documents
real time
cache misses
main memory
query processing