Po-Han Wang

Publication Activity (10 Years)

Years Active: 2009-2018
Publications (10 Years): 5

Top Topics

Design Space Exploration

Gpu Implementation

Access Patterns

Memory Bandwidth

Top Venues

IEEE Comput. Archit. Lett.

Publications

Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. DAC (2018)
Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang
Enabling fast preemption via Dual-Kernel support on GPUs. ASP-DAC (2017)
Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. IEEE Comput. Archit. Lett. 16 (2) (2017)
Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. ISPASS (2017)
Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture. DAC (2016)
Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky
Full system simulation framework for integrated CPU/GPU architecture. VLSI-DAT (2014)
Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng
A cycle-level SIMT-GPU simulation framework. ISPASS (2012)
Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen, Yu-Jung Cheng
Power gating strategies on GPUs. ACM Trans. Archit. Code Optim. 8 (3) (2011)
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
PM-COSYN: PE and memory co-synthesis for MPSoCs. DATE (2010)
Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang, Yu-Jung Cheng
A Predictive Shutdown Technique for GPU Shader Processors. IEEE Comput. Archit. Lett. 8 (1) (2009)