Chih-Yuan Lu

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 24

Top Topics

Content Addressable

Experimental Study

Hamming Distance

Top Venues

VLSI Technology and Circuits

Publications

Po-Hao Tseng, Yu-Hsuan Lin, Feng-Min Lee, Tian-Cig Bo, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu
Reliability Assessment for an In-3D-NAND Approximate Searching Solution. IRPS (2024)
Hang-Ting Lue, Wei-Chen Chen, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu
DRAM Below Equivalent 10nm Node. IMW (2024)
Wei-Chen Chen, Hang-Ting Lue, Ming-Hung Wu, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu
Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection. IMW (2024)
Po-Hao Tseng, Shao-Yu Fang, Yu-Hsuan Lin, Feng-Ming Lee, Jhe-Yi Liao, Yu-Yu Lin, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu
3D-NAND based Filtering Cube with High Resolution 2D Query and Tunable Feature Length for Computational SSD. IMW (2024)
Pei-Ci Jhang, Chi-Pin Lu, Jung-Yu Shieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Hang-Ting Lue, Pei-Ying Du, Chih-Yuan Lu
Charge Loss Improvement in 3D Flash Memory by Molecular Oxidation of Tunneling Oxide. IRPS (2024)
Wei-Chen Chen, Hang-Ting Lue, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu
A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. IMW (2023)
Po-Hao Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, Feng-Ming Lee, Yu-Yu Lin, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu
SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories. IMW (2023)
Chih-Chang Hsieh, Hang-Ting Lue, Yung-Chun Li, Shuo-Nan Hung, Chun-Hsiung Hung, Keh-Chung Wang, Chih-Yuan Lu
Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance. VLSI Technology and Circuits (2023)
Cheng-Lin Sung, Sheng-Ting Fan, Hang-Ting Lue, Wei-Chen Chen, Pei-Ying Du, Teng-Hao Yeh, Keh-Chung Wang, Chih-Yuan Lu
First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures. IRPS (2022)
Po-Hao Tseng, Yu-Hsuan Lin, Feng-Ming Lee, Tian-Cig Bo, Yung-Chun Li, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu
In-Memory Approximate Computing Architecture Based on 3D-NAND Flash Memories. VLSI Technology and Circuits (2022)
Yu-Hsuan Lin, Po-Hao Tseng, Feng-Min Lee, Ming-Hsiu Lee, Chih-Chang Hsieh, Dai-Ying Lee, Keh-Chung Wang, Chih-Yuan Lu
NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing. IMW (2022)
Han-Wen Hu, Wei-Chen Wang, Yuan-Hao Chang, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Ming Huang, Chong-Ying Lee, Tzu-Hsiang Su, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Chung Kuang Chen, Han-Sung Chen, Hsiang-Pang Li, Tei-Wei Kuo, Meng-Fan Chang, Keh-Chung Wang, Chun-Hsiung Hung, Chih-Yuan Lu
ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration. MICRO (2022)
Han-Wen Hu, Wei-Chen Wang, Chung Kuang Chen, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Chao Lin, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Han-Sung Chen, Yuan-Hao Chang, Hsiang-Pang Li, Tei-Wei Kuo, Keh-Chung Wang, Meng-Fan Chang, Chun-Hsiung Hung, Chih-Yuan Lu
A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices. ISSCC (2022)
Cheng-Lin Sung, Hang-Ting Lue, Wei-Chen Chen, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu
First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits. IMW (2021)
Hang-Ting Lue, Han-Wen Hu, Tzu-Hsuan Hsu, Po-Kai Hsu, Keh-Chung Wang, Chih-Yuan Lu
Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator. ISCAS (2021)
Ming-Liang Wei, Hussam Amrouch, Cheng-Lin Sung, Hang-Ting Lue, Chia-Lin Yang, Keh-Chung Wang, Chih-Yuan Lu
Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses. IRPS (2021)
Hang-Ting Lue, Tzu-Hsuan Hsu, Cheng-Lin Sung, Teng-Hao Yeh, Keh-Chung Wang, Chih-Yuan Lu
Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances. IMW (2021)
Chieh Roger Lo, Teng-Hao Yeh, Wei-Chen Chen, Hang-Ting Lue, Keh-Chung Wang, Chih-Yuan Lu, Yao-Wen Chang, Yung-Hsiang Chen, Chu-Yung Liu
Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution. IRPS (2020)
Hang-Ting Lue, Po-Kai Hsu, Keh-Chung Wang, Chih-Yuan Lu
Introduction of Non-Volatile Computing In Memory (nvCIM) by 3D NAND Flash for Inference Accelerator of Deep Neural Network (DNN) and the Read Disturb Reliability Evaluation : (Invited Paper). IRPS (2020)
Nian-Jia Wang, Kuan-Yi Lee, Hsin-Yi Lin, Wei-Hao Hsiao, Ming-Yi Lee, Li-Kuang Kuo, Ding-Jhang Lin, Yen-Hai Chao, Chih-Yuan Lu
Statistical Analysis of Bit-Errors Distribution for Reliability of 3-D NAND Flash Memories. IRPS (2020)
Wei-Hao Hsiao, Nian-Jia Wang, Ming-Yi Lee, Li-Kuang Kuo, Ding-Jhang Lin, Yen-Hai Chao, Chih-Yuan Lu
Modeling of Apparent Activation Energy and Lifetime Estimation for Retention of 3D SGVC Memory. IRPS (2019)
T. W. Lin, S. H. Ku, C. H. Cheng, C. W. Lee, Ijen Huang, Wen-Jer Tsai, T. C. Lu, W. P. Lu, K. C. Chen, Tahui Wang, Chih-Yuan Lu
Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. IRPS (2018)
Ming-Yi Lee, T.-Y. Chang, W.-F. Hsueh, Li-Kuang Kuo, Ding-Jhang Lin, Yen-Hai Chao, U. J. Tzeng, Chih-Yuan Lu
Electrical method to localize the high-resistance of nanoscale CoSi2 word-line for OTP memories. IRPS (2018)
Y. H. Liu, H. Y. Lin, C. M. Jiang, Tahui Wang, W. J. Tsai, T. C. Lu, K. C. Chen, Chih-Yuan Lu
Investigation of data pattern effects on nitride charge lateral migration in a charge trap flash memory by using a random telegraph signal method. IRPS (2018)
Chun-Hsiung Hung, Meng-Fan Chang, Yih-Shan Yang, Yao-Jen Kuo, Tzu-Neng Lai, Shin-Jang Shen, Jo-Yu Hsu, Shuo-Nan Hung, Hang-Ting Lue, Yen-Hao Shih, Shih-Lin Huang, Ti-Wen Chen, Tzung Shen Chen, Chung Kuang Chen, Chi-Yu Hung, Chih-Yuan Lu
Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations. IEEE J. Solid State Circuits 50 (6) (2015)
Yan Polansky, Avi Lavan, Ran Sahar, Oleg Dadashev, Yoram Betser, Guy Cohen, Eduardo Maayan, Boaz Eitan, Ful-Long Ni, Yen-Hui Joseph Ku, Chih-Yuan Lu, Tim Chang-Ting Chen, Chun-Yu Liao, Chin-Hung Chang, Chung Kuang Chen, Wen-Chiao Ho, Yite Shih, Wenchi Ting, Wenpin Lu
A 4b/cell NROM 1Gb Data-Storage Memory. ISSCC (2006)
Chih-Yuan Lu
Non-volatile Semiconductor Memory Technology in Nanotech Era. MTDT (2006)