A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device.
Wei-Chen ChenHang-Ting LueTzu-Hsuan HsuKeh-Chung WangChih-Yuan LuPublished in: IMW (2023)
Keyphrases
- simulation study
- cmos technology
- metal oxide semiconductor
- field effect transistors
- high density
- low voltage
- embedded dram
- silicon on insulator
- leakage current
- low power
- dynamic random access memory
- integrated circuit
- monte carlo
- low cost
- parallel processing
- computer controlled
- power consumption
- nm technology
- main memory
- neural network
- real time
- image sensor
- steady state
- high speed