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K. C. Chen
ORCID
Publication Activity (10 Years)
Years Active: 1989-2023
Publications (10 Years): 4
Top Topics
Lot Size
Flash Memory
Multi Echelon
Storage Devices
Top Venues
IRPS
IIAI-AAI
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Publications
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Y. L. Chou
,
W. J. Tsai
,
G. W. Wu
,
W. Chang
,
T. C. Lu
,
K. C. Chen
,
C. Y. Lu
A Novel Data Recovery Technique for 3D TLC NAND Flash Memory Using Intercell Program.
IRPS
(2023)
T. W. Lin
,
S. H. Ku
,
C. H. Cheng
,
C. W. Lee
,
Ijen Huang
,
Wen-Jer Tsai
,
T. C. Lu
,
W. P. Lu
,
K. C. Chen
,
Tahui Wang
,
Chih-Yuan Lu
Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory.
IRPS
(2018)
Y. H. Liu
,
H. Y. Lin
,
C. M. Jiang
,
Tahui Wang
,
W. J. Tsai
,
T. C. Lu
,
K. C. Chen
,
Chih-Yuan Lu
Investigation of data pattern effects on nitride charge lateral migration in a charge trap flash memory by using a random telegraph signal method.
IRPS
(2018)
Z. H. Che
,
K. C. Chen
,
Y. L. Huang
,
Y. G. Liu
,
S. H. Yeh
A Hybrid Methodology for Multi-Echelon Supply Chain Network Planning with Production Loss.
IIAI-AAI
(2016)
K. C. Chen
Session MP4b: Machine-to-machine communications and networks (invited).
ACSCC
(2012)
Pablo Robelly
,
Hendrik Seidel
,
K. C. Chen
,
Gerhard P. Fettweis
Energy efficiency vs. programmability trade-off: architectures and design principles.
DATE
(2006)
Wern-Ho Sheen
,
K. C. Chen
,
Fumiyuki Adachi
Editorial.
Wirel. Pers. Commun.
17 (1) (2001)
Anmol Mathur
,
K. C. Chen
,
C. L. Liu
Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs.
FPGA
(1995)
Anmol Mathur
,
K. C. Chen
,
C. L. Liu
Re-engineering of timing constrained placements for regular architectures.
ICCAD
(1995)
C. Y. Ko
,
K. C. Chen
,
C. C. Lu
Performance of slotted ALOHA in multiple joint cells of wireless networks.
PIMRC
(1992)
S. Muroga
,
X. Q. Xiang
,
J. Limqueco
,
L. P. Lin
,
K. C. Chen
A logic network synthesis system, SYLON.
ICCD
(1989)