Sunil R. Das

Publication Activity (10 Years)

Years Active: 1972-2022
Publications (10 Years): 7

Top Topics

Data Compression

Discrete Wavelet Transform

Top Venues

Int. J. Image Graph.

IEEE Trans. Instrum. Meas.

Publications

William Sukaria, James Malasa, Shiu Kumar, Rahul Kumar, Mansour H. Assaf, Voicu Groza, Emil M. Petriu, Sunil R. Das
Epileptic Seizure Detection Using Convolution Neural Networks. MeMeA (2022)
Komal Chand, Kavilash Chand, Rahul Kumar, Bibhya Sharma, Mansour H. Assaf, Sunil R. Das, Voicu Groza, Emil M. Petriu, Satyendra N. Biswas
An Optimized Tongue Drive System for Disabled Persons. I2MTC (2021)
Samrat P. Khadilkar, Sunil R. Das, Mansour H. Assaf, Satyendra N. Biswas
Face Identification Based on Discrete Wavelet Transform and Neural Networks. Int. J. Image Graph. 19 (4) (2019)
Mohammad Nazmus Sakib, Rakibul Hassan, Satyendra N. Biswas, Sunil R. Das
Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Ezekiel Bokolonga, Martin Hauhana, Nicholas Rollings, David Aitchison, Mansour H. Assaf, Sunil R. Das, Satyendra N. Biswas, Voicu Groza, Emil M. Petriu
A compact multispectral image capture unit for deployment on drones. I2MTC (2016)
Satyanand Singh, Mansour H. Assaf, Sunil R. Das, Satyendra N. Biswas, Emil M. Petriu, Voicu Groza
Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm. I2MTC (2016)
Sunil R. Das, Abdullah-Al Amin, Satyendra N. Biswas, Mansour H. Assaf, Emil M. Petriu, Voicu Groza
An algorithm for generating prime implicants. I2MTC (2016)
Nicholas A. Malan, Sunil R. Das, Satyendra N. Biswas, Mansour H. Assaf, Scott Morton, Emil M. Petriu, Voicu Groza
Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations. I2MTC (2015)
Amit Kumar, Mansour H. Assaf, Sunil R. Das, Satyendra N. Biswas, Emil M. Petriu, Voicu Groza
Image processing based system for classification of vehicles for parking purposes. I2MTC (2015)
Shashisekhar Ramagundam, Sunil R. Das, Scott Morton, Satyendra N. Biswas, Voicu Groza, Mansour H. Assaf, Emil M. Petriu
Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture. I2MTC (2014)
Satyendra N. Biswas, Sunil R. Das, Emil M. Petriu
On System-on-Chip Testing Using Hybrid Test Vector Compression. IEEE Trans. Instrum. Meas. 63 (11) (2014)
Satyendra N. Biswas, Touhidul Hasan, Shuvashis DasGupta, Sunil R. Das, Voicu Groza, Emil M. Petriu, Mansour H. Assaf
Compressed video watermarking technique. I2MTC (2013)
Sunil R. Das, Danny L. Shaw, Satyendra N. Biswas, Mansour H. Assaf, Scott Morton, Irem Ozkarahan, Emil M. Petriu, Voicu Groza
Data compression using mixed cascade of nonlinear logic. I2MTC (2013)
Altaf Hossain, Voicu Groza, Sunil R. Das
Aliasing-Free Space Compaction in VLSI with Cascade of Two-Input OR/NOR Logic. DELTA (2011)
Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Mehmet Sahinoglu
On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing. IEEE Trans. Instrum. Meas. 57 (10) (2008)
Satyendra N. Biswas, Sunil R. Das, Mansour H. Assaf
A Novel Technique for Input Vector Compression in System-on-Chip Testing. ICIT (2008)
Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu
Aliasing-free compaction revisited. IET Circuits Devices Syst. 2 (1) (2008)
Sunil R. Das, Jila Zakizadeh, Satyendra Biswas, Mansour H. Assaf, Amiya Nayak, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach. IEEE Trans. Instrum. Meas. 56 (3) (2007)
Sunil R. Das, Rochit Rajsuman
Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing - Future of Semiconductor Test. IEEE Trans. Instrum. Meas. 55 (2) (2006)
Satyendra Biswas, Sunil R. Das, Emil M. Petriu
Space compactor design in VLSI circuits based on graph theoretic concepts. IEEE Trans. Instrum. Meas. 55 (4) (2006)
Jianxun Liu, Wen-Ben Jone, Sunil R. Das
Crosstalk test pattern generation for dynamic programmable logic arrays. IEEE Trans. Instrum. Meas. 55 (4) (2006)
Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization. IEEE Trans. Instrum. Meas. 54 (5) (2005)
Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das
A built-in self-testing method for embedded multiport memory arrays. IEEE Trans. Instrum. Meas. 54 (5) (2005)
Sunil R. Das, Rochit Rajsuman
Guest Editorial First Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT in the Area of VLSI Testing - Future of Semiconductor Test. IEEE Trans. Instrum. Meas. 54 (5) (2005)
Sunil R. Das
Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware. IEEE Trans. Instrum. Meas. 54 (3) (2005)
Satyendra Biswas, Sunil R. Das, Emil M. Petriu
An adaptive compressed MPEG-2 video watermarking scheme. IEEE Trans. Instrum. Meas. 54 (5) (2005)
Mehmet Sahinoglu, David L. Libby, Sunil R. Das
Measuring availability indexes with small samples for component and network reliability using the Sahinoglu-Libby probability model. IEEE Trans. Instrum. Meas. 54 (3) (2005)
Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
Fault simulation and response compaction in full scan circuits using HOPE. IEEE Trans. Instrum. Meas. 54 (6) (2005)
Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu
Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. IWDC (2004)
Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu
Aliasing-Free Compaction in Testing Cores-Based System-on-Chip (SoC) using Compatibility of Response Data outputs. Trans. SDPS 8 (1) (2004)
Mansour H. Assaf, Sunil R. Das, Emil M. Petriu, Mehmet Sahinoglu
Enhancing Testability in Architectural Design for the New Generation of Core-Based Embedded Systems. HASE (2004)
Emil M. Petriu, Stephen K. S. Yeung, Sunil R. Das, Ana-Maria Cretu, Hans J. W. Spoelder
Robotic tactile recognition of pseudorandom encoded objects. IEEE Trans. Instrum. Meas. 53 (5) (2004)
Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza, Mehmet Sahinoglu
Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment. CIT (2004)
Vikram Arora, Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das
A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. 53 (4) (2004)
Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza
JBits Implementation and Design Verification in Space Compressor Design of Digital Circuits. Modelling, Identification and Control (2003)
Emil M. Petriu, Lichen Zhao, Sunil R. Das, Voicu Z. Groza, Aurel Cornell
Instrumentation applications of multibit random-data representation. IEEE Trans. Instrum. Meas. 52 (1) (2003)
Sunil R. Das, Rochit Rajsuman
Guest editorial [Special section on innovations in VLSI automatic test equipment (ATEs)]. IEEE Trans. Instrum. Meas. 52 (5) (2003)
Wen-Ben Jone, Der-Chen Huang, Sunil R. Das
An efficient BIST method for non-traditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. 52 (5) (2003)
Sunil R. Das, M. Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty, Mehmet Sahinoglu
Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets. IEEE Trans. Instrum. Meas. 52 (5) (2003)
Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, Sujoy Mukherjee
Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability. IWDC (2002)
Sunil R. Das, Jing Yi Liang, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Krishnendu Chakrabarty
Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering. IEEE Trans. Instrum. Meas. 51 (1) (2002)
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. VLSI Design (2001)
Sunil R. Das
Guest Editorial. VLSI Design 2001 (4) (2001)
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. VLSI Design (2001)
Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das
Random Pattern Testability Enhancement by Circuit Rewiring. VLSI Design 2001 (4) (2001)
Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das
An adaptive path selection method for delay testing. IEEE Trans. Instrum. Meas. 50 (5) (2001)
Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone
Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities. IEEE Trans. Instrum. Meas. 50 (6) (2001)
Sunil R. Das, Tony F. Barakat, Emil M. Petriu, Mansour H. Assaf, Krishnendu Chakrabarty
Space compression revisited. IEEE Trans. Instrum. Meas. 49 (3) (2000)
Krishnendu Chakrabarty, Sunil R. Das
Test-set embedding based on width compression for mixed-mode BIST. IEEE Trans. Instrum. Meas. 49 (3) (2000)
Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak
Syndrome Signature in Output Compaction for VLSI Built-in Self-Test. VLSI Design 1998 (2) (1998)
Sunil R. Das, Emil M. Petriu, Tony F. Barakat, Mansour H. Assaf, Amiya R. Nayak
Space compaction under generalized mergeability. IEEE Trans. Instrum. Meas. 47 (5) (1998)
Wen-Ben Jone, Sunil R. Das
A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. VLSI Design (1998)
Emil M. Petriu, Sunil R. Das, Niculaie Trif, Stephen S. K. Yeung
Pseudorandom encoding for structured light applications. CATA (1998)
Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
Delay Fault Coverage Enhancement Using Multiple Test Observation Times. VLSI Design (1997)
Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
Delay Fault Coverage Enhancement Using Variable Observation Times. J. Electron. Test. 11 (2) (1997)
Wen-Ben Jone, Nigam Shah, Anita Gleason, Sunil R. Das
PGEN: A Novel Approach to Sequential Circuit Test Generation. VLSI Design 4 (3) (1996)
Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak
Syndrome signature in output compaction for VLSI BIST. VLSI Design (1996)
Sunil R. Das
Guest Editorial. VLSI Design 4 (3) (1996)
Wen-Ben Jone, Sunil R. Das
CACOP-a random pattern testability analyzer. IEEE Trans. Syst. Man Cybern. 25 (5) (1995)
Sunil R. Das, Wen-Ben Jone, Amiya R. Nayak, Ian Choi
On testing of sequential machines using circuit decomposition and stochastic modeling. IEEE Trans. Syst. Man Cybern. 25 (3) (1995)
Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak
An improved output compaction technique for built-in self-test in VLSI circuits. VLSI Design (1995)
Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi
On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. VLSI Design (1994)
Amiya R. Nayak, Wen-Ben Jone, Sunil R. Das
Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach. ICPADS (1994)
Sunil R. Das
Guest Editorial. VLSI Design 1 (1) (1993)
Wen-Ben Jone, Sunil R. Das
CACOP - A Random Pattern Testability Analyzer. VLSI Design (1993)
Sunil R. Das, Wen-Ben Jone
On random testing for combinational circuits with a high measure of confidence. IEEE Trans. Syst. Man Cybern. 22 (4) (1992)
Sunil R. Das, Amiya Nayak
A survey on bit dimension optimization strategies of microprograms. MICRO (1990)
Sunil R. Das, Wen-Ben Jone, K. L. Wong
Probabilistic modeling and fault analysis in sequential logic using computer simulation. IEEE Trans. Syst. Man Cybern. 20 (2) (1990)
Wen-Ben Jone, Sunil R. Das
Multiple-output parity bit signature for exhaustive testing. J. Electron. Test. 1 (2) (1990)
Sunil R. Das, Ping Chao, Zen Chen, Yow Lung Dai, Mrinal K. Das
Transition submatrices in regular homing experiments and identification of sequential machines of known class using direct-sum transition matrices. Comput. Oper. Res. 14 (5) (1987)
Sunil R. Das
On random testing of sequential digital logic with a high confidence measure (abstract). ACM Conference on Computer Science (1986)
Sunil R. Das, S. Y. Lee
An appraisal of the performance of the MMSC subgraph generation algorithm on a Cyber System 170/720. Computing 37 (4) (1986)
Sunil R. Das, C. L. Sheng, Zen Chen, W. J. Hsu
Transition matrices in the measurement and control of synchronous sequential machines. Inf. Sci. 18 (1) (1979)
Sunil R. Das, C. L. Sheng
Strong connectivity in symmetric graphs and generation of maximal minimally strongly connected subgraphs. Inf. Sci. 14 (3) (1978)
N. S. Khabra, Sunil R. Das
Multiform Partial Symmetry and Linearity. IEEE Trans. Computers 22 (8) (1973)
Sunil R. Das, Narinder Singh Khabra
Clause-Column Table Approach for Generating All the Prime Implicants of Switching Functions. IEEE Trans. Computers 21 (11) (1972)