Cell-based layout techniques supporting gate-level voltage scaling for low power.
Chingwei YehYin-Shuin KangPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2000)
Keyphrases
- low power
- cmos technology
- low cost
- power consumption
- high speed
- low voltage
- energy dissipation
- wireless transmission
- single chip
- nm technology
- high power
- logic circuits
- digital signal processing
- vlsi circuits
- vlsi architecture
- low power consumption
- power dissipation
- power reduction
- hardware and software
- delay insensitive
- low complexity
- power system