Cell-based layout techniques supporting gate-level voltage scaling for low power.
Chingwei YehYin-Shuin KangPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2001)
Keyphrases
- low power
- cmos technology
- high speed
- power consumption
- low cost
- low voltage
- energy dissipation
- nm technology
- single chip
- high power
- wireless transmission
- digital signal processing
- logic circuits
- power system
- low power consumption
- vlsi architecture
- vlsi circuits
- delay insensitive
- image sensor
- gate array
- field effect transistors
- power reduction
- hardware and software
- signal processor
- signal processing