Power reduction through iterative gate sizing and voltage scaling.

Chingwei Yeh Min-Cheng Chang Shih-Chieh Chang Wen-Ben Jone

Published in: ISCAS (1) (1999)

Keyphrases

power reduction
power losses
power consumption
low power
cmos technology
low voltage
power saving
silicon dioxide
low cost
field effect transistors
power dissipation
real time
energy efficiency
energy saving
electric field
high speed
hidden markov models
image processing