A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications.
Chien-Chang LinJia-Wei ChenHsiu-Cheng ChangYao-Chang YangYi-Huan Ou-YangMing-Chih TsaiJiun-In GuoJinn-Shyan WangPublished in: IEEE J. Solid State Circuits (2007)
Keyphrases
- video decoder
- power consumption
- low power consumption
- video codec
- bitstream
- knowledge base
- low power
- video conferencing
- video coding
- video compression
- memory subsystem
- bit rate
- motion compensation
- compression algorithm
- embedded systems
- low cost
- platform independent
- video quality
- high speed
- low bit rate
- visual quality
- inter frame
- transform domain
- multiscale
- image processing
- real time