Yao-Chang Yang

Publication Activity (10 Years)

Years Active: 2006-2011
Publications (10 Years): 0

Publications

Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC (2011)
Chih-Chuan Yang, Kheng-Joo Tan, Yao-Chang Yang, Jiun-In Guo
Low complexity fractional motion estimation with adaptive mode selection for H.264/AVC. ICME (2010)
Yao-Chang Yang, Jiun-In Guo
High-Throughput H.264/AVC High-Profile CABAC Decoder for HDTV Applications. IEEE Trans. Circuits Syst. Video Technol. 19 (9) (2009)
Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo
A Dynamic Quality-scalable H.264 Video Encoder. ISCAS (2009)
Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang
A dynamic quality-scalable H.264 video encoder chip. ASP-DAC (2009)
Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shyan Wang, Jiun-In Guo
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. ISSCC (2007)
Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. SiPS (2007)
Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang, Ming-Chih Tsai, Jiun-In Guo, Jinn-Shyan Wang
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. IEEE J. Solid State Circuits 42 (1) (2007)
Yao-Chang Yang, Chien-Chang Lin, Hsui-Cheng Chang, Ching-Lung Su, Jiun-In Guo
A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing. ICME (2006)
Ching-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao-Chang Yang, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng
A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC. APCCAS (2006)