A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.
Cheng-An ChienYao-Chang YangHsiu-Cheng ChangJia-Wei ChenCheng-Yen ChangJiun-In GuoJinn-Shyan WangChing-Hwa ChengPublished in: ASP-DAC (2011)
Keyphrases
- video decoder
- bitstream
- scalable video
- coding scheme
- bit rate
- video quality
- compression algorithm
- video codec
- scalable video coding
- low power consumption
- video transmission
- compressed video
- high speed
- compressed domain
- video coding
- frame rate
- end to end
- rate distortion
- macroblock
- low cost
- base layer
- video signals
- error concealment
- wavelet coefficients
- real time
- enhancement layer
- packet loss
- low bit rate
- coding efficiency
- video streaming
- low power
- power consumption
- computational complexity