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Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques.

Chung-Hsun HuangJinn-Shyan WangYan-Chao Huang
Published in: IEEE J. Solid State Circuits (2002)
Keyphrases
  • design process
  • computer aided
  • learning environment
  • circuit design
  • real time
  • neural network
  • case study
  • control system
  • low cost
  • building blocks
  • software architecture
  • power consumption
  • priority scheduling