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A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop.
Jinn-Shyan Wang
Chun-Yuan Cheng
Je-Ching Liu
Yu-Chia Liu
Yi-Ming Wang
Published in:
IEEE J. Solid State Circuits (2010)
Keyphrases
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low power
duty cycle
mixed signal
power consumption
low cost
high speed
power dissipation
clock frequency
single chip
real time
multi channel
logic circuits
digital signal processing
low power consumption
energy efficiency
image sensor