Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.
Ching-Hwa ChengJinn-Shyan WangShih-Chieh ChangWen-Ben JonePublished in: DFT (2000)
Keyphrases
- high speed
- analog vlsi
- delay insensitive
- circuit design
- power dissipation
- test cases
- vlsi circuits
- low power
- fault model
- focal plane
- fault diagnosis
- power consumption
- cmos technology
- low cost
- low voltage
- real time
- test generation
- test suite
- chip design
- charge coupled devices
- software testing
- logic circuits
- parallel processing
- information sharing
- power supply
- analog circuits
- abnormal events
- scan data
- knowledge sharing
- charge coupled device
- built in self test