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A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.
Wen-Ben Jone
Christos A. Papachristou
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1995)
Keyphrases
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vlsi circuits
generation method
test cases
low power
test data
test suite
test generation
test sequences
testing process
software testing
mixed signal
statistical tests
high speed
test data generation
digital circuits
power dissipation