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An on-chip march pattern generator for testing embedded memory cores.
Wei-Lun Wang
Kuen-Jong Lee
Jhing-Fa Wang
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2001)
Keyphrases
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dynamic random access memory
pattern generator
processor core
level parallelism
memory subsystem
embedded dram
ibm power processor
random access memory
low cost
operating system
memory bandwidth
computing power
embedded systems
memory access
memory requirements
high speed
test cases