Soon-Jyh Chang

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 27

Top Topics

Detection Mechanism

Radially Symmetric

Top Venues

Publications

Kai-Cheng Cheng, Soon-Jyh Chang, Chung-Chieh Chen, Shuo-Hong Hung
-Order Noise-Shaping SAR ADC with Dynamic-Amplifier-Assisted Cascaded Integrator. ISSCC (2024)
Lih-Yih Chiou, Hong-Ming Shih, Shun-Hsiu Hsu, Zu-Cheng Sheng, Soon-Jyh Chang
Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator. ISCAS (2024)
Yi-Hu Wang, Soon-Jyh Chang
A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew Calibration. ISSCC (2023)
Jun-Hui Fu, Soon-Jyh Chang
A 12TOPS/W Computing-in-Memory Accelerator for Convolutional Neural Networks. ISCAS (2022)
Yi-Ying Chen, Soon-Jyh Chang
A Physically Unclonable Function Embedded in a SAR ADC. ITC-Asia (2022)
Che-Wei Hsu, Soon-Jyh Chang
A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration. ISCAS (2021)
Yu-Sian Lin, Soon-Jyh Chang, Chia-Ling Wei
A Noise-shaping SAR Assisted MASH 2-1 Sigma-Delta Modulator. VLSI-DAT (2020)
Kai-Min Chang, Yen-Ju Lin, Chia-Liang Wei, Soon-Jyh Chang
Resistor-Based Temperature Sensing Chip with Digital Output. VLSI-DAT (2020)
Tzung-Min Tsai, Shuenn-Yuh Lee, Soon-Jyh Chang
Detection System for Capacitive Plantar Pressure Monitoring. IEEE Access 8 (2020)
Chia-Chuan Li, Soon-Jyh Chang
Modified BER Test for SAR ADCs. ITC-Asia (2020)
Yi-Shen Cheng, Huan-Jui Hu, Soon-Jyh Chang
A 2-GS/s 8b Flash-SAR Time-Interleaved ADC with Background Offset Calibration. ISCAS (2019)
Huan-Jui Hu, Yi-Shen Cheng, Soon-Jyh Chang
A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC. ISCAS (2019)
Chung-Wei Hsu, Soon-Jyh Chang, Chun-Po Huang, Li-Jen Chang, Ya-Ting Shyu, Chih-Huei Hou, Hwa-An Tseng, Chih-Yuan Kung, Huan-Jui Hu
A 12-b 40-MS/s Calibration-Free SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2018)
Yen-Long Lee, Yu-Po Cheng, Soon-Jyh Chang, Hsin-Wen Ting
A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs. IEEE Des. Test 35 (1) (2018)
Wen-Chia Luo, Soon-Jyh Chang, Chun-Po Huang, Hao-Sheng Wu
A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process. VLSI-DAT (2018)
Chih-Yuan Kung, Chun-Po Huang, Chia-Chuan Li, Soon-Jyh Chang
A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window. ISCAS (2018)
Chung-Wei Hsu, Li-Jen Chang, Chun-Po Huang, Soon-Jyh Chang
A 12-bit 40-MS/s calibration-free SAR ADC. ISCAS (2017)
Yen-Long Lee, Soon-Jyh Chang
A quick jitter tolerance estimation technique for bang-bang CDRs. ITC-Asia (2017)
Yen-Long Lee, Soon-Jyh Chang, Yen-Chi Chen, Yu-Po Cheng
An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits. IEEE Trans. Circuits Syst. II Express Briefs (5) (2017)
Ming-Hung Chien, Yen-Long Lee, Jih Ren Goh, Soon-Jyh Chang
A low power duobinary voltage mode transmitter. ISLPED (2017)
Chih-Huei Hou, Soon-Jyh Chang, Hao-Sheng Wu, Huan-Jui Hu, En-Ze Cun
An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator. VLSI-DAT (2017)
I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting
Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Wen-Tze Chen, Ya-Ting Shyu, Chun-Po Huang, Soon-Jyh Chang
A pipeline ADC with latched-based ring amplifiers. ISCAS (2016)
Chun-Po Huang, Hsin-Wen Ting, Soon-Jyh Chang
Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs. IEEE Trans. Instrum. Meas. 65 (8) (2016)
Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang
A Systematic Design Methodology of Asynchronous SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (10) (2016)
Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. ASP-DAC (2016)
Jih Ren Goh, Yen-Long Lee, Soon-Jyh Chang
A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. VLSI-DAT (2015)
An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, Soon-Jyh Chang
A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS. Int. J. Circuit Theory Appl. 43 (10) (2015)
Shuenn-Yuh Lee, Tzung-Min Tsai, Wei-Chih Lai, Soon-Jyh Chang, Stony Tai
A 925 MHz 1.4μW wireless energy-harvesting circuit with error-correction ASK demodulation for RFID healthcare system. ISCAS (2015)
Wei-Hao Tsai, Che-Hsun Kuo, Soon-Jyh Chang, Li-Tse Lo, Ying-Cheng Wu, Chun-Jen Chen
A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems. ISCAS (2015)
Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, Soon-Jyh Chang
A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer. VLSI-DAT (2015)
I-Jen Chao, Ching-Wen Hou, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang
A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder. IEICE Trans. Electron. (6) (2014)
Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Yen-Chi Chen, Jih Ren Goh, Chung-Ming Huang
An area- and power-efficient half-rate clock and data recovery circuit. ISCAS (2014)
Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, Che-Hsun Kuo
A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. ISCAS (2014)
Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
A 10b 100kS/s SAR ADC with charge recycling switching method. A-SSCC (2014)
Tzung-Min Tsai, Hsing-Chen Lin, Shuenn-Yuh Lee, Soon-Jyh Chang
Heart rate detection through bone-conduction headset. BioCAS (2014)
An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, Soon-Jyh Chang
A Low-Cost Stimulus Design for Linearity Test in SAR ADCs. IEICE Trans. Electron. (6) (2014)
Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, Guan-Ying Huang
Low power pipelined SAR ADC with loading-free architecture. VLSI-DAT (2014)
Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, Soon-Jyh Chang
A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 21 (4) (2013)
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
I-Jen Chao, Chia-Ming Kuo, Bin-Da Liu, Chun-Yueh Huang, Soon-Jyh Chang
A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique. ISCAS (2013)
Ting-Zi Chen, Soon-Jyh Chang, Guan-Ying Huang
A successive approximation ADC with resistor-capacitor hybrid structure. VLSI-DAT (2013)
Sheng-Hsiung Lin, Jin-Fu Lin, Guan-Ying Huang, Soon-Jyh Chang
A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology. APCCAS (2012)
Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, Soon-Jyh Chang
Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. ICCAD (2012)
Ya-Ting Shyu, Ying-Zu Lin, Rong-Sing Chu, Guan-Ying Huang, Soon-Jyh Chang
A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin
A power-efficient sizing methodology of SAR ADCs. ISCAS (2012)
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications. IEEE J. Solid State Circuits 47 (11) (2012)
Ren-Li Chen, Soon-Jyh Chang
A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications. IEEE Trans. Circuits Syst. II Express Briefs (11) (2012)
Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, Jin-Fu Lin
A 1-V CDS bandgap reference without on-chip resistors. APCCAS (2012)
Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Ren-Li Chen, Hsin-Wen Ting, Soon-Jyh Chang
Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers. IET Circuits Devices Syst. 6 (2) (2012)
I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting
A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing. IEICE Trans. Electron. (11) (2012)
Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, Chin-Fu Lin
A 1-V, 44.6 ppm/°C bandgap reference with CDS technique. VLSI-DAT (2012)
Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang
Routability-driven placement algorithm for analog integrated circuits. ISPD (2012)
An-Sheng Chao, Soon-Jyh Chang, Hsin-Wen Ting
A SAR ADC BIST for simplified linearity test. SoCC (2011)
Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. DAC (2011)
Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, Chun-Cheng Liu
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. A-SSCC (2011)
Hsin-Wen Ting, Soon-Jyh Chang, Su-Ling Huang
A Design of Linearity Built-in Self-Test for Current-Steering DAC. J. Electron. Test. 27 (1) (2011)
Jin-Fu Lin, Soon-Jyh Chang
A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages. IEICE Trans. Electron. (1) (2011)
Jin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting, Chih-Hao Huang
Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang
Performance-driven analog placement considering boundary constraint. DAC (2010)
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2010)
Jin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu, Chih-Hao Huang
A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique. IEEE Trans. Circuits Syst. II Express Briefs (3) (2010)
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. ISSCC (2010)
Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang
A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme. IEEE Trans. Very Large Scale Integr. Syst. 18 (3) (2010)
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. IEEE J. Solid State Circuits 45 (4) (2010)
An-Sheng Chao, Soon-Jyh Chang
A Jitter Characterizing BIST with Pulse-Amplifying Technique. Asian Test Symposium (2009)
Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang
Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique. Asian Test Symposium (2009)
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. ISSCC (2009)
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu
A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process. IEICE Trans. Electron. (2) (2009)
Soon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu
A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR. IEEE Trans. Circuits Syst. II Express Briefs (11) (2008)
Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang
A Histogram-Based Testing Method for Estimating A/D Converter Performance. IEEE Trans. Instrum. Meas. 57 (2) (2008)
Hsin-Hung Ou, Soon-Jyh Chang, Bin-Da Liu
Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Chia-Ling Wei, Lu-Yao Wu, Hsiu-Hui Yang, Chien-Hung Tsai, Bin-Da Liu, Soon-Jyh Chang
A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter. IEICE Trans. Electron. (5) (2008)
Jin-Fu Lin, Te-Chieh Kung, Soon-Jyh Chang
A Reduced Code Linearity Test Method for Pipelined A/D Converters. ATS (2008)
Hsin-Hung Ou, Bin-Da Liu, Soon-Jyh Chang
A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture. IEICE Trans. Electron. (9) (2008)
Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang
A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS. CICC (2007)
Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. J. Electron. Test. 23 (6) (2007)
Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang
Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. ISCAS (2006)
Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang
Histogram Based Testing Strategy for ADC. ATS (2006)
Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang
An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. APCCAS (2006)
Jin-Fu Lin, Soon-Jyh Chang
A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. ISCAS (2006)
Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang
A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. Asian Test Symposium (2004)
Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang
A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. Asian Test Symposium (2004)
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. 19 (4) (2003)
Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng
A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. Asian Test Symposium (2003)
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electron. Test. 18 (6) (2002)
Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang, Jwu E. Chen
A DFT for semi-DC fault diagnosis for switched-capacitor circuits. ETW (1999)
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
Functional test pattern generation for CMOS operational amplifier. VTS (1997)