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Yen-Long Lee
ORCID
Publication Activity (10 Years)
Years Active: 2014-2018
Publications (10 Years): 4
Top Topics
High Power
Logic Circuits
Delay Insensitive
Accurate Estimation
Top Venues
ITC-Asia
IEEE Des. Test
IEEE Trans. Circuits Syst. II Express Briefs
ISLPED
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Publications
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Yen-Long Lee
,
Yu-Po Cheng
,
Soon-Jyh Chang
,
Hsin-Wen Ting
A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs.
IEEE Des. Test
35 (1) (2018)
Yen-Long Lee
,
Soon-Jyh Chang
A quick jitter tolerance estimation technique for bang-bang CDRs.
ITC-Asia
(2017)
Yen-Long Lee
,
Soon-Jyh Chang
,
Yen-Chi Chen
,
Yu-Po Cheng
An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
(5) (2017)
Ming-Hung Chien
,
Yen-Long Lee
,
Jih Ren Goh
,
Soon-Jyh Chang
A low power duobinary voltage mode transmitter.
ISLPED
(2017)
Jih Ren Goh
,
Yen-Long Lee
,
Soon-Jyh Chang
A dual-edge sampling CES delay-locked loop based clock and data recovery circuits.
VLSI-DAT
(2015)
Yen-Long Lee
,
Soon-Jyh Chang
,
Rong-Sing Chu
,
Yen-Chi Chen
,
Jih Ren Goh
,
Chung-Ming Huang
An area- and power-efficient half-rate clock and data recovery circuit.
ISCAS
(2014)