A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique.
Jin-Fu LinSoon-Jyh ChangChun-Cheng LiuChih-Hao HuangPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2010)
Keyphrases
- low power
- analog to digital converter
- mixed signal
- low cost
- power consumption
- high speed
- single chip
- image sensor
- vlsi circuits
- wireless transmission
- high power
- digital signal processing
- low power consumption
- transmission line
- power supply
- data flow
- logic circuits
- nm technology
- vlsi architecture
- real time
- multi channel
- cmos image sensor
- instruction set architecture