Low power pipelined SAR ADC with loading-free architecture.
Jia-Jhang WuSoon-Jyh ChangSheng-Hsiung LinChun-Po HuangGuan-Ying HuangPublished in: VLSI-DAT (2014)
Keyphrases
- low power
- vlsi architecture
- single chip
- power consumption
- low cost
- high speed
- analog to digital converter
- cmos technology
- mixed signal
- wireless transmission
- high power
- digital signal processing
- image sensor
- nm technology
- signal processor
- real time
- parallel architecture
- data flow
- low power consumption
- vlsi circuits
- cmos image sensor
- logic circuits
- synthetic aperture radar
- power reduction
- image reconstruction
- sigma delta
- gate array
- linear array
- vlsi implementation
- low complexity
- bit rate