A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages.
Jin-Fu LinSoon-Jyh ChangPublished in: IEICE Trans. Electron. (2011)
Keyphrases
- low power
- power consumption
- back end
- vlsi architecture
- high power
- low cost
- power management
- high speed
- single chip
- power saving
- cmos technology
- power reduction
- user friendly
- analog to digital converter
- wireless transmission
- low power consumption
- management system
- data types
- data management
- signal processor
- vlsi circuits
- ultra low power
- nm technology
- gate array
- logic circuits
- power dissipation
- building blocks
- delay insensitive
- energy dissipation
- data mining
- real time
- mixed signal
- multi channel
- user interface