A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window.
Cheng-Hsun HoSoon-Jyh ChangGuan-Ying HuangChe-Hsun KuoPublished in: ISCAS (2014)
Keyphrases
- low power
- analog to digital converter
- single chip
- power consumption
- high speed
- low cost
- mixed signal
- image sensor
- synthetic aperture radar
- logic circuits
- vlsi circuits
- high power
- sar images
- low power consumption
- wireless transmission
- digital signal processing
- cmos technology
- vlsi architecture
- image reconstruction
- nm technology