Cheng-Wu Lin

Publication Activity (10 Years)

Years Active: 2007-2020
Publications (10 Years): 2

Top Topics

Power Reduction

Integrated Circuit

Metal Oxide Semiconductor

Top Venues

Int. J. Circuit Theory Appl.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Cheng-Wu Lin, Shanq-Jang Ruan, Wei-Chun Hsu, Ya-Wen Tu, Shao-Li Han
Optimizing the Sensor Placement for Foot Plantar Center of Pressure without Prior Knowledge Using Deep Reinforcement Learning. Sensors 20 (19) (2020)
An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, Soon-Jyh Chang
A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS. Int. J. Circuit Theory Appl. 43 (10) (2015)
An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, Soon-Jyh Chang
A Low-Cost Stimulus Design for Linearity Test in SAR ADCs. IEICE Trans. Electron. (6) (2014)
Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 21 (4) (2013)
Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, Soon-Jyh Chang
Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. ICCAD (2012)
Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin
A power-efficient sizing methodology of SAR ADCs. ISCAS (2012)
Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang
Routability-driven placement algorithm for analog integrated circuits. ISPD (2012)
Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. DAC (2011)
Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang
Performance-driven analog placement considering boundary constraint. DAC (2010)
Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang
A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme. IEEE Trans. Very Large Scale Integr. Syst. 18 (3) (2010)
Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. J. Electron. Test. 23 (6) (2007)