Ying-Zu Lin

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 6

Top Topics

Introductory Computer

Power Reduction

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yueh-hui Vanessa Chiang, Ying-Zu Lin, Nian-Shing Chen
Using deep learning models to predict student performance in introductory computer programming courses. ICALT (2022)
Yueh-hui Vanessa Chiang, Ying-Zu Lin, Nian-Shing Chen
An investigation of group, rater and ratee effects on peer-/self-assessments in a collaborative learning environment in higher education: a cross-classified multilevel analysis. ICALT (2021)
Chin-Yu Lin, Ying-Zu Lin, Chih-Hou Tsai, Chao-Hsin Lu
An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI Process. ISSCC (2021)
Ying-Zu Lin, Chin-Yu Lin, Shan-Chih Tsou, Chih-Hou Tsai, Chao-Hsin Lu
A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET. ISSCC (2019)
Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu
A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS. VLSI Circuits (2016)
Chun-Cheng Liu, Che-Hsun Kuo, Ying-Zu Lin
A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS. IEEE J. Solid State Circuits 50 (11) (2015)
Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
A 10b 100kS/s SAR ADC with charge recycling switching method. A-SSCC (2014)
Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, Soon-Jyh Chang
A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 21 (4) (2013)
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Ya-Ting Shyu, Ying-Zu Lin, Rong-Sing Chu, Guan-Ying Huang, Soon-Jyh Chang
A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications. IEEE J. Solid State Circuits 47 (11) (2012)
Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, Chun-Cheng Liu
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. A-SSCC (2011)
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2010)
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. ISSCC (2010)
Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang
A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme. IEEE Trans. Very Large Scale Integr. Syst. 18 (3) (2010)
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. IEEE J. Solid State Circuits 45 (4) (2010)
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. ISSCC (2009)
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu
A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process. IEICE Trans. Electron. (2) (2009)
Soon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu
A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR. IEEE Trans. Circuits Syst. II Express Briefs (11) (2008)
Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang
A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS. CICC (2007)