A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology.

Sheng-Hsiung Lin Jin-Fu Lin Guan-Ying Huang Soon-Jyh Chang

Published in: APCCAS (2012)

Keyphrases

cmos technology
low power
spl times
power consumption
parallel processing
low voltage
single chip
high speed
sar images
low cost
data flow
mixed signal
power dissipation
parallel architecture
image sensor
silicon on insulator
digital signal processing
linear array
optical flow