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Kun-Lun Luo
Publication Activity (10 Years)
Years Active: 2004-2016
Publications (10 Years): 1
Top Topics
Architectural Design
Cost Effectiveness
User Friendly
Back End
Top Venues
Asian Test Symposium
J. Electron. Test.
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Publications
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Kun-Lun Luo
,
Ming-Hsueh Wu
,
Chun-Lung Hsu
,
Chen-An Chen
Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM.
J. Electron. Test.
32 (2) (2016)
Bing-Chuan Bai
,
Chun-Lung Hsu
,
Ming-Hsueh Wu
,
Chen-An Chen
,
Yee-Wen Chen
,
Kun-Lun Luo
,
Liang-Chia Cheng
,
James Chien-Mo Li
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.
Asian Test Symposium
(2013)
Chen-An Chen
,
Yee-Wen Chen
,
Chun-Lung Hsu
,
Ming-Hsueh Wu
,
Kun-Lun Luo
,
Bing-Chuan Bai
,
Liang-Chia Cheng
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.
Asian Test Symposium
(2013)
Chin-Lung Su
,
Rei-Fu Huang
,
Cheng-Wen Wu
,
Kun-Lun Luo
,
Wen Ching Wu
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories.
IEEE Trans. Very Large Scale Integr. Syst.
19 (12) (2011)
Shih-Ping Lin
,
Chung-Len Lee
,
Jwu-E Chen
,
Ji-Jan Chen
,
Kun-Lun Luo
,
Wen Ching Wu
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.
IEEE Trans. Very Large Scale Integr. Syst.
15 (7) (2007)
Shih Ping Lin
,
Chung-Len Lee
,
Jwu E. Chen
,
Ji-Jan Chen
,
Kun-Lun Luo
,
Wen Ching Wu
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.
ITC
(2006)
Rei-Fu Huang
,
Chin-Lung Su
,
Cheng-Wen Wu
,
Shen-Tien Lin
,
Kun-Lun Luo
,
Yeong-Jar Chang
Fail Pattern Identification for Memory Built-In Self-Repair.
Asian Test Symposium
(2004)