Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design.
Shi-Rou LinWei-Hung LinShih-Hsu HuangChun-Lung HsuChi-Tien SunPublished in: ICCE-TW (2020)
Keyphrases
- low power
- hardware architecture
- high speed
- single chip
- low power consumption
- power consumption
- low cost
- vlsi architecture
- logic circuits
- gate array
- vlsi circuits
- digital signal processing
- hardware implementation
- design process
- hardware architectures
- power dissipation
- cmos technology
- high power
- real time
- field programmable gate array
- design methodology
- signal processing
- mixed signal
- wireless transmission