Po-Chang Tsai

Publication Activity (10 Years)

Years Active: 2005-2008
Publications (10 Years): 0

Publications

Po-Chang Tsai, Sying-Jyan Wang
Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction. IET Comput. Digit. Tech. 2 (6) (2008)
Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture. ATS (2007)
Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh
Test Data Compression for Minimum Test Application Time. J. Inf. Sci. Eng. 23 (6) (2007)
Po-Chang Tsai, Sying-Jyan Wang
Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction. ATS (2006)
Po-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang
FSM-based programmable memory BIST with macro command. MTDT (2005)