Tung-Hua Yeh

Publication Activity (10 Years)

Years Active: 2007-2017
Publications (10 Years): 1

Top Topics

Load Forecasting

Computer Assisted Language Learning

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

David Pursley, Tung-Hua Yeh
High-level low-power system design optimization. VLSI-DAT (2017)
Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC (2014)
Tung-Hua Yeh, Sying-Jyan Wang
Power-Aware High-Level Synthesis With Clock Skew Management. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Tung-Hua Yeh, Sying-Jyan Wang
Thermal Safe High Level Test Synthesis for Hierarchical Testability. Asian Test Symposium (2010)
Sying-Jyan Wang, Tung-Hua Yeh
High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (10) (2009)
Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh
Test Data Compression for Minimum Test Application Time. J. Inf. Sci. Eng. 23 (6) (2007)
Sying-Jyan Wang, Tung-Hua Yeh
High-level test synthesis for delay fault testability. DATE (2007)