Xiaole Cui

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 50

Top Topics

Calibration Method

Top Venues

Sci. China Inf. Sci.

Publications

Feng Wei, Xiaole Cui, Sunrui Zhang
An in-Array Build-In Self-Test Scheme for Embedded SRAM Array. IEEE Trans. Circuits Syst. II Express Briefs 71 (8) (2024)
Shengjie Zhou, Yongliang Chen, Xiaole Cui, Yun Liu
Modeling Attack Tests and Security Enhancement of the Sub-Threshold Voltage Divider Array PUF. DATE (2024)
Yongliang Chen, Xiaole Cui, Xiaoxin Cui, Xing Zhang
The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice. Microelectron. J. 144 (2024)
Feng Wei, Xiaole Cui, Sunrui Zhang, Xing Zhang
An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Yuanyuan Jiang, Li Lun, Jiawei Wang, Mingqi Yin, Hanqing Liu, Zhenhui Dai, Xiaole Cui, Xiaoxin Cui
SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow. ISCAS (2024)
Chen Wei, Xiaole Cui, Xiaoxin Cui
Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays. IEEE Trans. Reliab. 73 (1) (2024)
Xiaole Cui, Mingqi Yin, Hanqing Liu, Xiaoxin Cui
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells. ACM Trans. Design Autom. Electr. Syst. 29 (1) (2024)
Yongliang Chen, Xiaole Cui, Yun Liu, Xiaoxin Cui
An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs. IEEE Trans. Inf. Forensics Secur. 18 (2023)
Sunrui Zhang, Xiaole Cui, Feng Wei, Xiaoxin Cui
An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array. IEEE Trans. Computers 72 (12) (2023)
Yongliang Chen, Xiaole Cui, Yun Liu, Xiaoxin Cui
An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs. IEEE Trans. Instrum. Meas. 72 (2023)
Xiaole Cui, Chen Wei, Xu Feng, Xiaoxin Cui
Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (5) (2023)
Yongliang Chen, Xiaole Cui, Pengyuan Yang, Gang Qu
An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic Gates. ICCAD (2023)
Xiaole Cui, Fan Liu, Sunrui Zhang, Xiaoxin Cui
An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells. ISCAS (2022)
Fan Liu, Sunrui Zhang, Xiaole Cui
The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates. FPL (2022)
Chen Wei, Xiaole Cui, Xiaoxin Cui
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec. IEEE Des. Test 39 (5) (2022)
Yun Liu, Yongliang Chen, Xiaole Cui
A Modeling Attack on the Sub-threshold Current Array PUF. HOST (2022)
Huixian Huang, Xiaole Cui, Shuming Zhang, Ge Li, Xiaoxin Cui
An obfuscation scheme of scan chain to protect the cryptographic chips. ATS (2022)
Yuqian Sun, Xiaole Cui, Yongliang Chen, Xiaoxin Cui
The logic obfuscation of LFSR with the crosstalk based polymorphic gate. AsianHOST (2021)
Qingyun Zou, Xiaoxin Cui, Zhenhui Dai, Yisong Kuang, Yi Zhong, Chenglong Zou, Xiaole Cui
28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance. IEICE Electron. Express 18 (20) (2021)
Kanglin Xiao, Xiaoxin Cui, Kefei Liu, Xiaole Cui, Xin'an Wang
An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor. IJCNN (2021)
Yi Zhong, Jianhua Feng, Xiaoxin Cui, Xiaole Cui
Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption. J. Comput. Sci. Technol. 36 (5) (2021)
Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui
The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack. ITC (2021)
Xiaole Cui, Yongliang Chen, Wenqiang Ye, Xiaoxin Cui
The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF. ITC-Asia (2021)
Xiaole Cui, Ye Ma, Feng Wei, Xiaoxin Cui
The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates. IEEE Access 9 (2021)
Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui
The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing. ACM Great Lakes Symposium on VLSI (2021)
Xiangyu Zhang, Feng Wei, Xiaoyan Liu, Xiaole Cui
Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array. ASICON (2021)
Xiaole Cui, Xiao Ma, Qiujun Lin, Xiang Li, Hang Zhou, Xiaoxin Cui
Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates. Circuits Syst. Signal Process. 39 (6) (2020)
Xiaole Cui, Qiujun Lin, Xiaoxin Cui, Feng Wei, Xiaoyan Liu, Jinfeng Kang
The synthesis method of logic circuits based on the iMemComp gates. Integr. 74 (2020)
Xiaole Cui, Xiao Ma, Feng Wei, Xiaoxin Cui
A synthesis method for logic circuits in RRAM arrays. Sci. China Inf. Sci. 63 (10) (2020)
Xianfeng Li, Gengchao Li, Xiaole Cui
ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy Optimizations. DAC (2020)
Li Qu, Xiaole Cui, Xiaoxin Cui
A Testability Enhancement Method for the Memristor Ratioed Logic Circuits. ATS (2020)
Runze Han, Peng Huang, Yudi Zhao, Xiaole Cui, Xiaoyan Liu, Jinfeng Kang
Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing. Sci. China Inf. Sci. 62 (2) (2019)
Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui
A Novel Polymorphic Gate Based Circuit Fingerprinting Technique. ACM Great Lakes Symposium on VLSI (2018)
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui
Design of Low-Power High-Performance FinFET Standard Cells. Circuits Syst. Signal Process. 37 (5) (2018)
Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui
Polymorphic gate based IC watermarking techniques. ASP-DAC (2018)
Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Xiaole Cui, Qiang Zhang, Xiaoxin Cui, Xin'an Wang, Jinfeng Kang, Xiaoyan Liu
R RRAM array with sneak path technique. Sci. China Inf. Sci. 60 (2) (2017)
Yewen Ni, Xiaoxin Cui, Tian Wang, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui
Improving DFA on AES using all-fault ciphertexts. ASICON (2017)
Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui
Improving DFA attacks on AES with unknown and random faults. Sci. China Inf. Sci. 60 (4) (2017)
Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui, Gang Qu
A practical cold boot attack on RSA private keys. AsianHOST (2017)
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui
High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ). IEEE Trans. Ind. Electron. 64 (1) (2017)
Kuimin Zhang, Xiaole Cui, Xiaoxin Cui
A design of high performance full adder with memristors. ASICON (2017)
Yewen Ni, Xiaoxin Cui, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui
Design of router for spiking neural networks. ASICON (2017)
Liwen Zhu, Xiaole Cui, Xiang Li, Xiaoxin Cui
A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm. ASICON (2017)
Xiaole Cui, Chunliang Liu, Guangyi Shi, Yufeng Jin
A new calibration method for MEMS accelerometers with genetic algorithm. RCAR (2017)
Xiaole Cui, Yichi Luo, Qiujun Lin, Xiaoxin Cui
A Heuristic Algorithm for Automatic Generation of March Tests. ATS (2017)
Xiaole Cui, Xiaoxin Cui, Yewen Ni, Min Miao, Yufeng Jin
An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias. IEEE Trans. Very Large Scale Integr. Syst. 25 (5) (2017)
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui
Ultralow-power high-speed flip-flop based on multimode FinFETs. Sci. China Inf. Sci. 59 (4) (2016)
Xiaole Cui, Zuolin Cheng, Chunglen Lee, Xinnan Lin, Yiqun Wei, Xiaogang Chen, Zhitang Song
A snake addressing scheme for phase change memory testing. Sci. China Inf. Sci. 59 (10) (2016)
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology. IEICE Trans. Electron. (8) (2016)
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui
Employing the mixed FBB/RBB in the design of FinFET logic gates. ASICON (2015)
Bingqiang Jing, Xiaole Cui, Yalin Ran, Yufeng Jin
Post-bond test for TSVs using voltage division. ASICON (2015)
Lifei Liu, Xiaole Cui, Yalin Ran, Xiaoxin Cui
A countermeasure for power analysis to scalar multiplication of ECC hardware. ASICON (2015)
Hupo Wei, Xiaole Cui, Qiang Zhang, Yufeng Jin
An enhanced decoder for multiple-bit error correcting BCH codes. ASICON (2015)
Xufeng Li, Ronggang Wang, Xiaole Cui, Wenmin Wang
Context-adaptive fast motion estimation of HEVC. ISCAS (2015)
Zuolin Cheng, Xiaole Cui, Xiaoxin Cui, Chung Len Lee
Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure. IET Comput. Digit. Tech. 9 (6) (2015)
Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. ASICON (2015)
Shijie Zhang, Xiaole Cui, Qiang Zhang, Yufeng Jin
A TSV repair method for clustered faults. ASICON (2015)
Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung-Len Lee
A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications. ASICON (2013)
Si Chen, Xiaole Cui, Chung-Len Lee
A novel test scheme for NAND flash memory based on built-in oscillator ring. ASICON (2013)
Xuan Yang, Xiaole Cui, Chao Wang, Chung-Len Lee
A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. ASICON (2013)
Xiangrong Zhang, Xiaole Cui, Bo Wang, Chung-Len Lee
A UWB mixer with a balanced wide band active balun using crossing centertaped inductor. ISCAS (2013)
Yibo He, Xiaole Cui, Chung-Len Lee, Xiaoxin Cui, Yufeng Jin
New DfT architectures for 3D-SICs with a wireless test port. ASICON (2013)
Weijia Ma, Xiaole Cui, Chung-Len Lee
Enhanced error correction against multiple-bit-upset based on BCH code for SRAM. ASICON (2013)
Xiaoxin Cui, Rui Li, Wei Wei, Juan Gu, Xiaole Cui
AHardware implementation of DES with combined countermeasure against DPA. ASICON (2013)
Jin Zha, Xiaole Cui, Chung-Len Lee
Modeling and testing of interference faults in the nano NAND Flash memory. DATE (2012)
Guangyi Shi, Yuexian Zou, Yufeng Jin, Xiaole Cui, Wen Jung Li
Towards HMM based human motion recognition using MEMS inertial sensors. ROBIO (2008)
Xiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm. APCCAS (2006)