Dunshan Yu

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 29

Top Topics

Biologically Inspired

Integrated Circuit

Top Venues

Sci. China Inf. Sci.

IEICE Trans. Commun.

Publications

Zhenhui Dai, Jiawei Wang, Yi Zhong, Kunyu Feng, Cheng Zhao, Yuanyuan Jiang, Peiyu Chen, Yuan Wang, Dunshan Yu, Xiaoxin Cui
An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. ISCAS (2024)
Yuxuan Zhao, Xinyan Cao, Jinlong Lin, Dunshan Yu, Xixin Cao
Multimodal Affective States Recognition Based on Multiscale CNNs and Biologically Inspired Decision Fusion Model. IEEE Trans. Affect. Comput. 14 (2) (2023)
Ye Zhou, Wengao Lu, Shanzhe Yu, Dunshan Yu, Yacong Zhang, Zhongjian Chen
A multichannel readout integrated circuit with column-wise pseudo differential extended counting ADCs for an uncooled infrared focal plane array based on silicon diodes. Microelectron. J. 139 (2023)
Yisong Kuang, Xiaoxin Cui, Chenglong Zou, Yi Zhong, Zhenhui Dai, Zilin Wang, Kefei Liu, Dunshan Yu, Yuan Wang
An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. ISCAS (2022)
Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. ISCAS (2021)
Ye Zhou, Shanzhe Yu, Wengao Lu, Dunshan Yu, Yacong Zhang, Zhongjian Chen
Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers. ASICON (2021)
Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68 (7) (2021)
Timothy Dunlap, Omid Aramoon, Gang Qu, Tian Wang, Xiaoxin Cui, Dunshan Yu
A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates. AsianHOST (2021)
Yuxuan Zhao, Jin Yang, Jinlong Lin, Dunshan Yu, Xixin Cao
A 3D Convolutional Neural Network for Emotion Recognition based on EEG Signals. IJCNN (2020)
Yinxuan Lyu, Jianhua Feng, Kai Zhu, Hongfei Ye, Dunshan Yu
Fully on-chip clock jitter and skew measurement scheme via incoherent subsampling. Microelectron. J. 96 (2020)
Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing. ASICON (2019)
Weijun Lu, Chao Geng, Dunshan Yu
A New Method for Futures Price Trends Forecasting Based on BPNN and Structuring Data. IEICE Trans. Inf. Syst. (9) (2019)
Qi Zhang, Jian Cao, Ying Zhang, Shiguang Zhang, Quan Zhang, Dunshan Yu
FPGA Implementation of Quantized Convolutional Neural Networks. ICCT (2019)
Hao Xie, Guoqing Xiang, Dunshan Yu, Hong Yu, Yuan Li, Wei Yan
Perceptual Fast CU Size Decision Algorithm for AVS2 Intra Coding. BigMM (2019)
Yuxuan Zhao, Xinyan Cao, Jinlong Lin, Dunshan Yu, Xixin Cao
Multimodal Emotion Recognition Model using Physiological Signals. CoRR (2019)
Lingjuan Wu, Wenqian Zhao, Dunshan Yu
Designing a 3D Graphics Processor for Mobile Applications. ASICON (2019)
Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui
A Novel Polymorphic Gate Based Circuit Fingerprinting Technique. ACM Great Lakes Symposium on VLSI (2018)
Yinxuan Lyu, Jianhua Feng, Chenfeng Tu, Linqi Shi, Hongfei Ye, Weixin Gai, Dunshan Yu
0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching. ISCAS (2018)
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui
Design of Low-Power High-Performance FinFET Standard Cells. Circuits Syst. Signal Process. 37 (5) (2018)
Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui
Polymorphic gate based IC watermarking techniques. ASP-DAC (2018)
Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui
Improving DFA attacks on AES with unknown and random faults. Sci. China Inf. Sci. 60 (4) (2017)
Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui, Gang Qu
A practical cold boot attack on RSA private keys. AsianHOST (2017)
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui
High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ). IEEE Trans. Ind. Electron. 64 (1) (2017)
Weijun Lu, Yanbin Zhang, Dengyun Lei, Dunshan Yu
Efficient Weak Signals Acquisition Strategy for GNSS Receivers. IEICE Trans. Commun. (1) (2016)
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui
Ultralow-power high-speed flip-flop based on multimode FinFETs. Sci. China Inf. Sci. 59 (4) (2016)
Yanbin Zhang, Weijun Lu, Ruiyuan Liu, Dunshan Yu
Improving tracking accuracy with subcarrier assistance and code monitoring for BOC modulated signal. Comput. Electr. Eng. 53 (2016)
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology. IEICE Trans. Electron. (8) (2016)
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui
Employing the mixed FBB/RBB in the design of FinFET logic gates. ASICON (2015)
Dengyun Lei, Weijun Lu, Yanbin Zhang, Dunshan Yu
Balance Differential Coherent Bit Synchronization Algorithm for GNSS Receiver. IEICE Trans. Commun. (6) (2015)
Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. ASICON (2015)
Kaisheng Ma, Xiaoxin Cui, Kai Liao, Nan Liao, Di Wu, Dunshan Yu
Key characterization factors of accurate power modeling for FinFET circuits. Sci. China Inf. Sci. 58 (2) (2015)
Dengyun Lei, Weijun Lu, Dunshan Yu
Resource-efficient acquisition architecture for BOC-modulated signals. IEICE Electron. Express 11 (11) (2014)
Nan Liao, Xiaoxin Cui, Kai Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu
Low power adiabatic logic based on FinFETs. Sci. China Inf. Sci. 57 (2) (2014)
Yanbin Zhang, WeiJun Lu, Dengyun Lei, Yongcan Huang, Dunshan Yu
Effective PPS Signal Generation with Predictive Synchronous Loop for GPS. IEICE Trans. Commun. (8) (2014)
Kai Liao, Xiaoxin Cui, Nan Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu
Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs. Sci. China Inf. Sci. 57 (4) (2014)
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Xiao Zhang, Ying Huang, Dunshan Yu
). ISCAS (2014)
Xiaoxin Cui, Kaisheng Ma, Kai Liao, Nan Liao, Di Wu, Wei Wei, Rui Li, Dunshan Yu
A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs. ISCAS (2013)
Lingjuan Wu, Ryan Kastner, Bo Gu, Dunshan Yu
Design of a Reconfigurable Acoustic Modem for Underwater Sensor Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2013)
Ran Fang, Wengao Lu, Guannan Wang, Tingting Tao, Yacong Zhang, Zhongjian Chen, Dunshan Yu
A Low-noise High-voltage Interface Circuit for capacitive MEMS gyroscope. J. Circuits Syst. Comput. 22 (9) (2013)
Ran Fang, Wengao Lu, Guannan Wang, Tingting Tao, Yacong Zhang, Zhongjian Chen, Dunshan Yu
A capacitive Interface Circuit with capacitor mismatch Auto-compensation for MEMS gyroscope. J. Circuits Syst. Comput. 22 (10) (2013)
Xun Jiang, Xiaoxin Cui, Dunshan Yu
A JTAG-based configuration circuit applied in SerDes chip. ASICON (2011)
Teng Lin, Jianhua Feng, Dunshan Yu
Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning. IEICE Trans. Inf. Syst. (5) (2009)
WeiJun Lu, Ying Li, Dunshan Yu, Xing Zhang
A Low Cost Correlator Structure in the Pseudo-Noise Code Acquisition System. IEICE Trans. Commun. (5) (2009)
Shiqun Zhang, Dunshan Yu, Shimin Sheng
A Discrete STFT Processor for Real-time Spectrum Analysis. APCCAS (2006)
Xixin Cao, Qingqing Xie, Chungan Peng, Qingchun Wang, Dunshan Yu
An Efficient VLSI Implementation of Distributed Architecture for DWT. MMSP (2006)
Xin Zhang, Dunshan Yu, Shimin Sheng
A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs. APCCAS (2006)
Xiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm. APCCAS (2006)