Yuan Wang

ORCID

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 80

Top Venues

ISCAS

IEEE Trans. Circuits Syst. II Express Briefs

ASICON

Sci. China Inf. Sci.

Publications

Qingyu Guo, Nanbing Pan, Xin Qiao, Xiaoxin Cui, Yuan Wang
OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Xin Qiao, Jiahao Song, Youming Yang, Renjie Wei, Xiyuan Tang, Meng Li, Runsheng Wang, Yuan Wang
MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks. CICC (2024)
Xin Qiao, Qingyu Guo, Xiyuan Tang, Jiahao Song, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang
A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (4) (2024)
Lindong Wu, Xuefei Lv, Shaoning Jin, Chaoyi Ban, Zongwei Wang, Yuan Wang, Yimao Cai
A cascaded timestamp-free event camera image compression method for gesture recognition. ISIE (2024)
Jiahao Song, Zihan Wu, Xiyuan Tang, Bocheng Xu, Haoyang Luo, Youming Yang, Yuan Wang, Runsheng Wang, Ru Huang
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing. ISSCC (2024)
Zhenhui Dai, Jiawei Wang, Yi Zhong, Kunyu Feng, Cheng Zhao, Yuanyuan Jiang, Peiyu Chen, Yuan Wang, Dunshan Yu, Xiaoxin Cui
An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. ISCAS (2024)
Lindong Wu, Zongwei Wang, Lin Bao, Linbo Shan, Zhizhen Yu, Yunfan Yang, Shuangjie Zhang, Guandong Bai, Cuimei Wang, John Robertson, Yuan Wang, Yimao Cai, Ru Huang
Investigation and mitigation of Mott neuronal oscillation fluctuation in spiking neural network. Sci. China Inf. Sci. 67 (2) (2024)
Zilong Shen, Jiaiun Tang, Haoyang Luo, Zhongyi Wu, Zongnan Wang, Xing Zhang, Xiyuan Tang, Yuan Wang
A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation. CICC (2024)
Haikang Diao, Haoyang Luo, Jiahao Song, Bocheng Xu, Runsheng Wang, Yuan Wang, Xiyuan Tang
A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. CICC (2024)
Kanglin Xiao, Xin Qiao, Xiaoxin Cui, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang
A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations. IEEE Trans. Circuits Syst. II Express Briefs 71 (7) (2024)
Tong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang
ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. CoRR (2024)
Kefei Liu, Jingjie Shang, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Kanglin Xiao, Yi Zhong, Yuan Wang
How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model. IEEE Trans. Cogn. Dev. Syst. 16 (3) (2024)
Xin Qiao, Youming Yang, Chang Xue, Yandong He, Xiaoxin Cui, Song Jia, Yuan Wang
An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 71 (5) (2024)
Tong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang
ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. DATE (2024)
Chang Xue, Xin Qiao, Xu Ren, Gang Du, Yuan Wang, Yandong He
A 768.7-2124.2 TOPS/W Time-Domain Computing-in-Memory Macro With Low Static Leakage and Precision-Configurable TDC. IEEE Trans. Circuits Syst. II Express Briefs 71 (5) (2024)
Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization. CICC (2023)
Jiahao Song, Xiyuan Tang, Xin Qiao, Yuan Wang, Runsheng Wang, Ru Huang
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (5) (2023)
Yuan Zhang, Jian Cao, Ling Zhang, Jue Chen, Wenyu Sun, Yuan Wang
Razor SNN: Efficient Spiking Neural Network with Temporal Embeddings. CoRR (2023)
Zilin Wang, Yi Zhong, Youming Yang, Xiaoxin Cui, Yuan Wang
An Efficient Spiking Neural Network Accelerator with Sparse Weight. BioCAS (2023)
Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang
Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation. AICAS (2023)
Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang
A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. IEEE Trans. Circuits Syst. II Express Briefs 70 (6) (2023)
Bingsen Wang, Jian Cao, Jue Chen, Shuo Feng, Yuan Wang
A New ANN-SNN Conversion Method with High Accuracy, Low Latency and Good Robustness. IJCAI (2023)
Kefei Liu, Xiaoxin Cui, Xiang Ji, Yisong Kuang, Chenglong Zou, Yi Zhong, Kanglin Xiao, Yuan Wang
Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips. IEEE Trans. Circuits Syst. II Express Briefs 70 (4) (2023)
Chenglong Zou, Xiaoxin Cui, Guang Chen, Yuanyuan Jiang, Yuan Wang
Toward a Lossless Conversion for Spiking Neural Networks with Negative-Spike Dynamics. Adv. Intell. Syst. 5 (12) (2023)
Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Yuan Wang, Runsheng Wang, Ru Huang
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. CICC (2023)
Yixuan Hu, Tengyu Zhang, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang, Ru Huang
Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion. DATE (2023)
Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. ISSCC (2023)
Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang
An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs 70 (11) (2023)
Zilin Wang, Yi Zhong, Xiaoxin Cui, Yisong Kuang, Yuan Wang
A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight. ISCAS (2023)
Xiaochen Hao, Zijian Ding, Jieming Yin, Yuan Wang, Yun Liang
Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators. ICCAD (2023)
Zilong Shen, Yize Wang, Yunhao Li, Xing Zhang, Yuan Wang
A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Nanbing Pan, Xin'an Wang, Yuan Wang
A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. ISCAS (2022)
Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang
A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. Microelectron. J. 126 (2022)
Chenglong Zou, Xiaoxin Cui, Yisong Kuang, Yuan Wang, Xinan Wang
A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition. AICAS (2022)
Chenglong Zou, Xiaoxin Cui, Guang Chen, Shuo Feng, Kefei Liu, Xinan Wang, Yuan Wang
Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor. Microelectron. J. 129 (2022)
Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang
A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Kefei Liu, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Yi Zhong, Kanglin Xiao, Yuan Wang
A Full-Neuron Memory Model Designed for Neuromorphic Systems. AICAS (2022)
Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang
A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations. ICTA (2022)
Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
Jiahao Song, Yuan Wang, Xiyuan Tang, Runsheng Wang, Ru Huang
A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing. A-SSCC (2021)
Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. ISCAS (2021)
Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68 (7) (2021)
Qingyu Guo, Yuan Wang, Xiaoxin Cui
Integer-Only Neural Network Quantization Scheme Based on Shift-Batch-Normalization. CoRR (2021)
Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang
A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. ISCAS (2021)
Yuan Wang, Sebin Gracy, Hideaki Ishii, Karl Henrik Johansson
Suppressing the endemic equilibrium in SIS epidemics: A state dependent approach. CoRR (2021)
Jiahao Song, Yuan Wang, Minguang Guo, Xiang Ji, Kaili Cheng, Yixuan Hu, Xiyuan Tang, Runsheng Wang, Ru Huang
TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Yawen Zhang, Runsheng Wang, Yixuan Hu, Weikang Qian, Yanzhi Wang, Yuan Wang, Ru Huang
Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network. ISCAS (2020)
Yize Wang, Guangyi Lu, Yuan Wang
A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. IEEE Access 8 (2020)
Yawen Zhang, Runsheng Wang, Xinyue Zhang, Yuan Wang, Ru Huang
Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators. IEEE Trans. Circuits Syst. (12) (2020)
Yawen Zhang, Sheng Lin, Runsheng Wang, Yanzhi Wang, Yuan Wang, Weikang Qian, Ru Huang
When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing. DATE (2020)
Yawen Zhang, Runsheng Wang, Xinyue Zhang, Zherui Zhang, Jiahao Song, Zuodong Zhang, Yuan Wang, Ru Huang
A Parallel Bitstream Generator for Stochastic Computing. CoRR (2019)
Xinyue Zhang, Yuan Wang, Yawen Zhang, Jiahao Song, Zuodong Zhang, Kaili Cheng, Runsheng Wang, Ru Huang
Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ICICDT (2019)
Zhao Zhao, Yuan Wang, Cheng Li, Xiaoxin Cui, Ru Huang
A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model. ICICDT (2019)
Yawen Zhang, Xinyue Zhang, Jiahao Song, Yuan Wang, Ru Huang, Runsheng Wang
Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing. SiPS (2019)
Xinyue Zhang, Jiahao Song, Yuan Wang, Yawen Zhang, Zuodong Zhang, Runsheng Wang, Ru Huang
An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ASICON (2019)
Lizhong Zhang, Yuan Wang, Yize Wang, Xing Zhang, Yandong He
Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection. Sci. China Inf. Sci. 62 (6) (2019)
Zhao Zhao, Yuan Wang, Xinyue Zhang, Xiaoxin Cui, Ru Huang
An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training. BioCAS (2019)
Weikang Qian, Runsheng Wang, Yuan Wang, Marc D. Riedel, Ru Huang
A Survey of Computation-Driven Data Encoding. SiPS (2019)
Cheng Li, Yuan Wang, Jin Zhang, Xiaoxin Cui, Ru Huang
A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition. BioCAS (2018)
Lu Zhang, Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang
A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation. ISCAS (2018)
Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. ISCAS (2018)
Yuan Wang, Mengyin Jiang, Baoguang Liu, Song Jia, Xing Zhang
A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process. Int. J. Circuit Theory Appl. 46 (8) (2018)
Yuan Wang, Guangyi Lu, Yize Wang, Xing Zhang
Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. IEICE Trans. Electron. (3) (2017)
Yize Wang, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. IEICE Electron. Express 14 (9) (2017)
Guangyi Lu, Yuan Wang, Yize Wang, Xing Zhang
Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. ISCAS (2017)
Yuan Wang, Yuequan Liu, Song Jia, Xing Zhang
Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process. Int. J. Circuit Theory Appl. 45 (6) (2017)
Yunfan Yang, Song Jia, Yuan Wang, Shaonan Zhang, Chao Liu
A reliable true random number generator based on novel chaotic ring oscillator. ISCAS (2017)
Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang
Compact digital-controlled neuromorphic circuit with low power consumption. ISCAS (2017)
Yukuai Chen, Jian Cao, Zhang Qihui, Yuan Wang, Xing Zhang
A novel equivalent circuit model of the surge wave generator. ASICON (2017)
Song Jia, Ziyi Wang, Shilin Yan, Yuan Wang
A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents. Int. J. Circuit Theory Appl. 44 (10) (2016)
Wenyi Tang, Song Jia, Yuan Wang
A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis. IEICE Trans. Electron. (8) (2016)
Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Xing Zhang
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. ISCAS (2016)
Jian Cao, Yize Wang, Yuan Wang, Guangyi Lu, Xing Zhang
A novel SPICE circuit model of electrostatic discharge (ESD) generator. IEICE Electron. Express 13 (9) (2016)
Guangyi Lu, Yuan Wang, Xing Zhang
Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. IEICE Trans. Electron. (5) (2016)
Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Xing Zhang
Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. Sci. China Inf. Sci. 59 (12) (2016)
Yuan Wang, Guangyi Lu, Haibing Guo, Jian Cao, Song Jia, Xing Zhang
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. 59 (4) (2016)
Yuan Wang, Yuequan Liu, Mengyin Jiang, Song Jia, Xing Zhang
Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics. ISCAS (2016)
Song Jia, Ziyi Wang, Zijin Li, Yuan Wang
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. ISCAS (2016)
Yuan Wang, Shanliang Gan, Song Jia, Xing Zhang
A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology. Int. J. Circuit Theory Appl. 44 (9) (2016)
Jian Cao, Jingya Xu, Yuan Wang, Guangyi Lu, Xing Zhang
A compact SCR model using advanced BJT models and standard SPICE elements. Sci. China Inf. Sci. 59 (10) (2016)
Jiyu Chen, Song Jia, Yuan Wang
A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier. ASICON (2015)
Song Jia, Shilin Yan, Yuan Wang, Ganggang Zhang
A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. ISCAS (2015)
Song Jia, Weiting Li, Wenyi Tang, Yuan Wang
A low power and high speed CAM design using pulsed voltage for search-line. ASICON (2015)
Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Song Jia, Xing Zhang
Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci. China Inf. Sci. 58 (4) (2015)
Yuequan Liu, Yuan Wang, Song Jia, Xing Zhang
180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance. ISCAS (2015)
Jian Cao, Zhenxu Ye, Yuan Wang, Guangyi Lu, Xing Zhang
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. ASICON (2015)
Mengyin Jiang, Yuan Wang, Baoguang Liu, Yuequan Liu, Song Jia, Xing Zhang
A reference-less all-digital burst-mode CDR with embedded TDC. ASICON (2015)
Yuan Wang, Wei Su, Guangliang Guo, Xing Zhang
Novel DEM Technique for Current-Steering DAC in 65-nm CMOS Technology. IEICE Trans. Electron. (12) (2015)
Nan Han, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. ASICON (2015)
Fangyuan Dang, Yuan Wang, Yuequan Liu, Song Jia, Xing Zhang
Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. ASICON (2015)
Peng Zhang, Yuan Wang, Xing Zhang, Xiaohua Ma, Yue Hao
Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp. Sci. China Inf. Sci. 57 (2) (2014)
Baoguang Liu, Yuan Wang, Guangliang Guo, Song Jia, Xing Zhang
A novel dynamic element match technique in current-steering DAC. ASICON (2013)
Fengfeng Wu, Song Jia, Qinglong Meng, Shigong Lv, Yuan Wang, Dacheng Zhang
Improved CRC Calculation Strategies for 64-bit Serial RapidIO. IEICE Trans. Electron. (10) (2013)
Song Jia, Heqing Xu, Fengfeng Wu, Yuan Wang
A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs. IEICE Trans. Electron. (9) (2013)
Song Jia, Li Liu, Xiayu Li, Fengfeng Wu, Yuan Wang, Ganggang Zhang
Data Convertors Design for Optimization of the DDPL Family. IEICE Trans. Electron. (9) (2013)
Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. ASICON (2013)
Yuan Wang, Baoguang Liu, Wei Su, Junlei Zhao, Xing Zhang
Thermo data-weighted average dynamic element matching (DEM) encoder for current-steering DACs. IEICE Electron. Express 10 (20) (2013)
Heqing Xu, Song Jia, Jiyu Chen, Yuan Wang, Gang Du
A current mode sense amplifier with self-compensation circuit for SRAM application. ASICON (2013)
Xiayu Li, Song Jia, Limin Liu, Yuan Wang
A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF). IEICE Trans. Electron. (6) (2012)
Xiayu Li, Song Jia, Limin Liu, Yuan Wang, Ganggang Zhang
Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application. Sci. China Inf. Sci. 55 (10) (2012)

Yuan Wang.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Yuan Wang